⚑ ELT 102 · Digital Logic & Solid State Devices Lesson 7 of 8
Unit 3 Β· Digital Foundations

Encoders, Decoders, Multiplexers & A/D-D/A Converters

Combinational building blocks that encode, route, and convert signals: encoders compress many lines into a code, decoders expand a code back to one line, multiplexers select and demultiplexers distribute β€” and ADCs/DACs carry signals across the analog-digital frontier.

⏱ 3 Hours Study πŸ“‹ 9 Core Topics πŸ“ Symbol Library (6 devices) πŸ“ˆ 3-Mode Conversion & Routing Lab

Learning Objectives

By the end of this lesson, you will be able to:

  • Explain the role of combinational MSI circuits in encoding, routing, and converting signals within digital systems.
  • Describe encoder operation β€” converting one active input line into a binary or BCD code β€” and explain how a priority encoder resolves multiple active inputs.
  • Analyze decoder operation, tracing an N-bit input to exactly one of 2α΄Ί activated output lines, and explain the function of the enable input.
  • Trace data through a multiplexer, using select lines to determine which of many inputs reaches the single output.
  • Contrast demultiplexer operation β€” distributing one input to a selected output β€” and explain how a decoder with a data input becomes a DEMUX.
  • Design conceptually a MUX/DEMUX data-transmission link that shares one channel among multiple signals (time-division multiplexing).
  • Explain the three steps of analog-to-digital conversion β€” sampling, quantizing, encoding β€” and calculate resolution as 2ⁿ levels.
  • Describe digital-to-analog conversion, the stepped output waveform, and why filtering smooths the reconstruction.
  • Match all six devices to real applications β€” keypads, memory address decoding, seven-segment displays, bus routing, sensor acquisition, and audio playback β€” and verify each behavior in the Conversion & Routing Lab.

Key Terms & Concepts

Click any card to reveal its definition.

Encoding & Decoding
Encoder
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
A combinational circuit that converts one active input line into a smaller coded output β€” e.g., an 8-to-3 encoder outputs the 3-bit binary code of whichever input is active. Many lines in, few coded bits out.
Priority Encoder
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
An encoder that resolves conflicts: if several inputs are active simultaneously, the highest-priority input wins and is encoded. A valid flag often indicates whether any input is present at all.
Decoder
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
The encoder's reverse: accepts an N-bit code and activates exactly one of up to 2α΄Ί output lines. A 3-to-8 decoder turns the code 101 into "output line 5 active, all others quiet."
Enable Input
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
A master on/off pin found on most decoders (and many MSI parts): when disabled, all outputs stay inactive regardless of the input code. Enables let decoders be cascaded and let address ranges be switched β€” the same gating idea as Lesson 6's latches.
BCD (Binary-Coded Decimal)
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
Each decimal digit 0–9 stored as its own 4-bit code. A decimal-to-BCD encoder converts a pressed keypad digit into its nibble; BCD-to-seven-segment decoders drive numeric displays.
Seven-Segment Display
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
Seven LED segments (a–g, from Lesson 2's optoelectronics) arranged as a figure-8. A decoder/driver translates a 4-bit code into the segment pattern for each digit β€” the classic decoder application on every multimeter and microwave.
MSI (Medium-Scale Integration)
Encoding & Decoding
πŸ”„ Click to reveal definition
Definition
The chip class housing this lesson's devices β€” tens to hundreds of gates packaged as one ready-made function (74HC148 encoder, 74HC138 decoder, 74HC151 MUX). Built entirely from Lesson 5's gates; used as single building blocks.
Signal Routing
Multiplexer (MUX)
Signal Routing
πŸ”„ Click to reveal definition
Definition
A data selector: chooses one of many inputs and forwards it to a single output, under the command of select lines. An 8-to-1 MUX funnels eight data paths into one channel.
Select Lines
Signal Routing
πŸ”„ Click to reveal definition
Definition
The address inputs that steer a MUX or DEMUX: n select lines address 2ⁿ channels (3 lines β†’ 8 inputs). The select code is read as a binary number naming the chosen channel β€” Lesson 5's place value at work.
Demultiplexer (DEMUX)
Signal Routing
πŸ”„ Click to reveal definition
Definition
The MUX's mirror: a data distributor that takes one input and routes it to one of several outputs chosen by select lines. The unselected outputs stay inactive.
Decoder-as-DEMUX
Signal Routing
πŸ”„ Click to reveal definition
Definition
Add a data line to a decoder's enable input and it becomes a demultiplexer: the select code picks the output, the data stream flows to it. One silicon layout, two catalog names β€” the 74138 is sold as both.
Bus
Signal Routing
πŸ”„ Click to reveal definition
Definition
A shared group of wires carrying data between many devices. MUXes decide who talks onto the bus, decoders decide who listens β€” the pairing that lets one set of wires serve a whole computer.
Time-Division Multiplexing
Signal Routing
πŸ”„ Click to reveal definition
Definition
Sharing one channel among many signals by rapidly scanning the select lines: each source gets the channel in turn, and a synchronized DEMUX sorts the slices back out. Watch it happen with the Lab's auto-scan.
Analog-Digital Conversion
ADC (Analog-to-Digital Converter)
A/D-D/A Conversion
πŸ”„ Click to reveal definition
Definition
Converts a continuous analog quantity (a voltage from a sensor or microphone) into a digital number, by sampling the input, quantizing it into discrete levels, and encoding the result as binary.
Sampling
A/D-D/A Conversion
πŸ”„ Click to reveal definition
Definition
Measuring the analog signal at regular instants β€” freezing snapshots of a moving waveform. The sampling rate must be fast enough to capture the signal's changes (at least twice its highest frequency), or the reconstruction misrepresents it.
Quantization
A/D-D/A Conversion
πŸ”„ Click to reveal definition
Definition
Rounding each sample to the nearest of 2ⁿ discrete levels. The rounding error (quantization error) is the price of going digital β€” shrink it by adding bits, since each extra bit doubles the number of levels.
Resolution
A/D-D/A Conversion
πŸ”„ Click to reveal definition
Definition
How finely a converter divides its range: n bits β†’ 2ⁿ levels, step size = range/2ⁿ. An 8-bit ADC on a 5 V range resolves ~19.5 mV; 12 bits resolves ~1.2 mV. Resolution and sampling rate together determine fidelity.
DAC (Digital-to-Analog Converter)
A/D-D/A Conversion
πŸ”„ Click to reveal definition
Definition
The reverse trip: converts a binary value into a proportional analog output, typically using weighted currents or voltage-divider (R-2R ladder) networks to reconstruct the signal.
Stepped (Staircase) Output
A/D-D/A Conversion
πŸ”„ Click to reveal definition
Definition
A DAC's raw output holds each value until the next sample arrives, producing a staircase waveform. A low-pass filter (op-amp circuits from Lesson 4!) smooths the steps into a continuous signal β€” the last stage of every audio output.

πŸ“ Device Symbol Library

Six devices, two visual families. Encoders, decoders, and converters are drawn as labeled rectangles — read the pin counts to identify them (many→few = encoder, few→many = decoder). Multiplexers and demultiplexers get the distinctive trapezoid: the wide side faces the many lines, the narrow side faces the one, and select lines enter from below.

I0-I7 Y2-Y0 ENC
Encoder (8-to-3)
One active input β†’ its 3-bit binary code Β· many in, few out
ActiveY2 Y1 Y0
I00 0 0
I30 1 1
I51 0 1
I71 1 1
A2-A0 EN Y0-Y7
Decoder (3-to-8)
N-bit code β†’ exactly one of 2α΄Ί lines active Β· EN=0 silences all
ENA2A1A0Active
0x x xnone
10 0 0Y0
11 0 1Y5
11 1 1Y7
D0D3 OUT S1 S0 MUX
Multiplexer (4-to-1)
Data selector Β· select lines choose which input reaches the one output
S1 S0OUT =
0 0D0
0 1D1
1 0D2
1 1D3
IN Y0Y3 S1 S0 DEMUX
Demultiplexer (1-to-4)
Data distributor Β· one input routed to the selected output
S1 S0IN goes to
0 0Y0
0 1Y1
1 0Y2
1 1Y3
ADC sampleΒ·quantizeΒ·encode n bits
ADC
Analog voltage in β†’ binary code out Β· resolution = 2ⁿ levels
BitsLevels
416
8256
124096
DAC reconstruct + filter n bits
DAC
Binary code in β†’ stepped analog out Β· filter smooths the staircase
Code (4-bit)Out (5V range)
00000.00 V
10002.50 V
11114.69 V

Core Lesson Content

Encoding, Routing, and Converting Signals

Lessons 5 and 6 gave you gates and memory. This lesson supplies the traffic system β€” combinational circuits that move information between forms and destinations. Every device here is built purely from Lesson 5's gates (no storage, no clock needed), yet each solves a problem so common it's sold as its own chip:

  • An encoder converts one active input line into a coded output, usually binary or BCD β€” compressing many wires into a few.
  • A decoder performs the reverse, taking an N-bit input and activating one of many output lines.
  • A multiplexer selects one of many inputs and sends it to a single output line.
  • A demultiplexer takes one input and routes it to one of many outputs.
  • An ADC converts an analog signal into a digital code, and a DAC converts a digital code back into an analog signal β€” the two doors between this course's analog half and its digital half.
πŸ’‘ One Mental Map for All Six
Think in pin counts and directions: encoder = many→few (compress) · decoder = few→many (expand) · MUX = many→one (select) · DEMUX = one→many (distribute) · ADC = analog→digital · DAC = digital→analog. Every application in this lesson is one of those six arrows.

Try It Live

Encoders: Many Lines In, a Code Out

What They Are

An encoder is a combinational circuit that converts an active input line into a smaller coded output. A basic encoder assumes only one input is active at a time: press one line, read its binary name. An 8-to-3 encoder watches eight input lines and outputs the 3-bit code of whichever is active.

How They Work

Input line 5 active (8-to-3 encoder) β†’ output = 101β‚‚   (the binary code for 5)

Internally it's just OR gates: each output bit ORs together every input line whose number has a 1 in that bit position. Y0 = I1+I3+I5+I7, Y1 = I2+I3+I6+I7, Y2 = I4+I5+I6+I7 β€” Lesson 5's place value implemented in gates.

The Priority Encoder

What if two keys are pressed at once? A basic encoder produces garbage (the OR gates merge both codes). A priority encoder resolves the conflict by encoding only the highest-priority active input, and typically adds a valid flag output indicating whether any input is present at all. This is the version real systems use β€” the 74HC148 in classic TTL, and the interrupt-priority logic inside every microprocessor.

Applications

  • Keyboard and keypad interfacing: 10 digit keys β†’ a 4-bit BCD code (decimal-to-BCD encoding), so the processor reads one nibble instead of scanning ten wires.
  • Octal-to-binary and other code conversions.
  • Input reduction wherever many signals must be compressed into fewer lines β€” sensor arrays, interrupt controllers, position encoders.
🎯 Lab Check
In the Lab's Encoder/Decoder mode, click input pad 5 and confirm the code lights read 101. Then press pads 3 and 4 together with priority OFF β€” the merged code 111 accuses innocent input 7. Enable Priority and 4 cleanly wins: that arbitration is the entire difference between the basic and priority versions.

Decoders: A Code In, One Line Out

What They Are

A decoder accepts an N-bit input and activates one of up to 2α΄Ί outputs β€” essentially the reverse of an encoder. A 2-to-4 decoder maps 2 input bits to 4 outputs; a 3-to-8 maps 3 bits to 8 lines. Many decoders include an enable input that turns the whole device on or off: when disabled, all outputs remain inactive regardless of the input code.

How They Work

For each binary input combination, exactly one output line is selected. Each output is an AND gate decoding its own address: Y5 = A2Β·A1̅Β·A0Β·EN fires only for code 101 with enable high. It's Lesson 5's truth-table thinking in silicon β€” one AND gate per row.

3-to-8 decoder, EN=1: input 101β‚‚ β†’ Y5 active, Y0–Y4 and Y6–Y7 all inactive
EN=0: all eight outputs inactive, whatever the code

Applications

  • Memory address decoding: the computer's address bus feeds decoders whose outputs are chip-select lines β€” the decoder decides which memory chip answers each address. Enable inputs let decoders cascade to cover huge address spaces.
  • Seven-segment display driving: a BCD-to-seven-segment decoder/driver converts each 4-bit digit into the a–g segment pattern lighting the LEDs (Lesson 2!) of a numeric display.
  • Data routing, device selection, and sequencing control β€” anywhere one-of-many must be chosen by a binary code.
πŸ’‘ The Round Trip
Encoder and decoder are inverse functions: encode input 5 β†’ code 101 β†’ decode β†’ output 5 lights. The Lab's Encoder/Decoder mode wires them back-to-back so you can watch the round trip live β€” the same trip every keypress takes into a processor and back out to a display.

Multiplexers: The Data Selector

What They Are

A multiplexer (MUX) is a data selector: it chooses one input from many and forwards it to one output. The choice is controlled by select lines, and the payoff is that a multiplexer reduces multiple data paths into a single channel.

How They Work

n select lines address 2ⁿ inputs:  2 lines β†’ 4-to-1 MUX  Β·  3 lines β†’ 8-to-1 MUX

The select code is read as a binary number naming the chosen channel: S1S0 = 10 connects input D2 to the output. Internally, gate networks (or transmission-gate structures in CMOS) route only the chosen input through β€” each data input is ANDed with its address decode, and the results are ORed into the single output.

Applications

  • Data selection in CPUs and digital systems: register-file reads, choosing between ALU sources β€” a processor is full of MUXes making choices every clock cycle.
  • Bus sharing and communication channel reduction: many devices, one set of wires; the MUX decides who transmits.
  • Implementing logic functions: a clever classic β€” wire a truth table's outputs to a MUX's data inputs, drive the select lines with the variables, and the MUX is the function. One 8-to-1 MUX can implement any 3-variable Boolean function from Lesson 5.
🎯 Quiz Tip
Select-line counts are pure Lesson 5 place value: 2ⁿ inputs need n select lines. 16-to-1 β†’ 4 lines; 32-to-1 β†’ 5. If an exam mentions a MUX with 3 select lines, it has 8 data inputs β€” no diagram required.

Demultiplexers: The Data Distributor

What They Are

A demultiplexer (DEMUX) is the multiplexer's mirror image: it takes one input and distributes it to one of several outputs β€” a one-to-many data distributor. Like the MUX, it uses select lines to choose the destination.

How They Work

The input signal is passed to only the selected output line; all other outputs remain inactive. Set S1S0 = 11 on a 1-to-4 DEMUX and whatever arrives at the input appears on Y3 alone.

πŸ’‘ The Decoder Connection
Compare the internals: a decoder activates one output per input code; a DEMUX routes data to one output per select code. They're the same circuit β€” add a data line to a decoder's enable input and the decoder becomes a demultiplexer. The 74HC138 is catalogued as both a "3-to-8 decoder" and a "1-of-8 demultiplexer" for exactly this reason. Recognizing shared structure like this is a mark of fluent schematic reading.

Applications

  • Data distribution to multiple destinations: one data source feeding whichever subsystem is addressed.
  • Serial-to-parallel style routing: incoming serial data steered into parallel destinations slot by slot.
  • Driving devices, memory write-lines, and output selection systems.

MUX + DEMUX: Sharing One Channel

Put the two mirrors face to face and you get one of digital communication's founding ideas. A MUX at the sending end funnels several signals into one shared channel; a DEMUX at the receiving end, driven by synchronized select lines, sorts them back out to their destinations.

Time-Division Multiplexing

Now scan the select lines rapidly β€” 00, 01, 10, 11, repeat. Each source gets the channel for a slice of time, and the receiver's DEMUX (stepping in lockstep) delivers each slice to the matching output. Four conversations share one wire, invisible to all four:

Sources D0–D3 β†’ [MUX] β†’ one channel β†’ [DEMUX] β†’ destinations Y0–Y3
Select lines scan 00β†’01β†’10β†’11β†’00… on both ends, synchronized
  • Why it matters: wires, connectors, and radio spectrum are expensive; select logic is cheap. Telephone trunks, digital audio interfaces, and sensor networks all ride on this trade.
  • The synchronization requirement is the hard part β€” if the two ends disagree about the select code, every message arrives at the wrong door. Real links send framing/clock information for exactly this reason (and Lesson 6's flip-flop synchronizers help tame it).
  • Scaling: the same structure with faster scanning and more channels is how thousands of calls share one fiber.
🎯 See It in the Lab
MUX/DEMUX mode has an Auto-Scan checkbox: switch it on and watch the select code sweep the four channels while the transmission path redraws in real time. Set different data values on D0–D3 first, and you'll see each value pop out of its own output in turn β€” time-division multiplexing, animated.

Analog-to-Digital Converters

Every real-world signal β€” temperature, sound, light, pressure β€” arrives as a continuous analog quantity, usually a voltage from one of the sensors and amplifier circuits you built in Lessons 1–4. An ADC converts that continuous voltage into a digital number the logic world can store and compute with. Three steps:

  1. Sampling: measure the input at regular instants β€” snapshots of a moving waveform. The sampling rate must be fast enough to capture the signal's changes (at least twice the highest signal frequency), or the reconstruction misrepresents the original.
  2. Quantizing: round each sample to the nearest of 2ⁿ discrete levels. The rounding error is the quantization error β€” the unavoidable price of going digital.
  3. Encoding: output each level as its binary code (Lesson 5's numbers, at last, coming from a real signal).

Resolution: The Bit Budget

n bits β†’ 2ⁿ levels  Β·  step size = range / 2ⁿ
8-bit ADC, 5 V range: 256 levels, ~19.5 mV steps  Β·  12-bit: 4096 levels, ~1.2 mV

The resolution and sampling rate together determine how accurately the signal is represented β€” each extra bit halves the step size, each doubling of sample rate captures faster changes. Both cost money and power, which is why choosing an ADC is always an engineering trade.

Applications

  • Microphones, sensors, and measurement instruments β€” your multimeter's entire front end is a careful ADC.
  • Data acquisition systems logging real-world signals for analysis.
  • Embedded controllers and communication systems that need digital processing of real-world signals.

Digital-to-Analog Converters

The DAC performs the reverse operation: it converts a binary value into a proportional analog output β€” the door back out of the digital world, to speakers, motors, displays, and control actuators.

How They Work

  • Weighted conversion networks: each bit contributes a current or voltage proportional to its place value β€” the MSB contributes half the range, the next bit a quarter, and so on. Practical designs use R-2R ladder voltage dividers (only two resistor values, easy to match) feeding a summing op-amp β€” the inverting amplifier from Lesson 4 doing the addition.
  • The stepped output: the raw output holds each converted value until the next code arrives, producing a staircase waveform.
  • Filtering: a low-pass filter smooths the steps into a continuous signal β€” the final handshake between digital data and the analog world.
4-bit DAC, 5 V range: code 1000β‚‚ (8) β†’ 8/16 Γ— 5 V = 2.50 V  Β·  1111β‚‚ (15) β†’ 15/16 Γ— 5 V β‰ˆ 4.69 V

Applications

  • Audio playback: every digital audio path ends in a DAC β€” millions of samples per second becoming a voltage that moves a speaker cone.
  • Signal generation and waveform synthesis: function generators compute waveforms digitally and DAC them into existence.
  • Control systems and actuator interfaces: a controller's computed output becomes the analog drive for valves, heaters, and motor speed references.
πŸ’‘ The Full-Circle Moment
Follow one voice through a phone call: microphone (analog) β†’ amplifier (Lesson 4) β†’ ADC β†’ codes routed by MUXes over shared channels (this lesson) stored in flip-flops (Lesson 6) β†’ DAC β†’ filter β†’ amplifier β†’ speaker (analog). Every lesson of this course is inside that one sentence.

The Six Devices, Side by Side

DeviceInputOutputMain FunctionTypical Uses
EncoderMany lines, usually one activeFewer coded bitsCompress input informationKeypads, code conversion
DecoderN-bit codeUp to 2α΄Ί linesExpand code to one active lineMemory decoding, displays
MultiplexerMany data inputsOne outputSelect one sourceBus routing, logic design
DemultiplexerOne inputMany outputsSend signal to one destinationData distribution, routing
ADCAnalog signalDigital codeSample and quantizeSensors, instruments
DACDigital codeAnalog signalReconstruct analog outputAudio, control, waveform generation

Where They Live Together

  • Memory systems: decoders select chips and rows; MUXes route data lines.
  • Displays: decoders drive segments; MUXes scan multiple digits over shared wires.
  • Communication: MUX/DEMUX pairs share channels; ADC/DAC pairs bookend every digital link that touches the physical world.
  • Sensors & audio: an analog MUX lets one ADC serve many sensors in turn; a DAC plus a Lesson 4 filter and amplifier completes the return path.
πŸ’‘ Course Thread
Diodes steered current (L1), supplies delivered it (L2), transistors switched it (L3), feedback refined it (L4), gates made it logical (L5), bistables gave it memory (L6) β€” and now the routing and conversion layer connects all of it to the real world. Lesson 8 assembles the full system.

πŸ“ˆ Interactive Conversion & Routing Lab

Three instruments in one panel. Encoder β†’ Decoder: press an input pad, watch its binary code form, and see the decoder light the matching output β€” the full round trip, with a priority-encoder toggle for multi-press conflicts. MUX β†’ DEMUX: set data values, steer the select lines, and watch one shared channel carry the chosen signal to the chosen destination β€” then enable Auto-Scan for live time-division multiplexing. ADC β†’ DAC: sample a real waveform, quantize it with your chosen bit depth, and compare the staircase reconstruction against the original.

πŸ’‘ The canvas is clickable β€” input pads and switches respond directly.

Priority encoder (multi-press allowed)
Auto-Scan (time-division mux)
Show DAC staircase reconstruction
πŸ’‘ Guided Explorations
1. The round trip: in Encoder/Decoder mode press pad 5 β€” code reads 101, decoder output 5 lights. Try every pad and confirm the code is always the pad's binary name. 2. The conflict: priority OFF, press 3 and 4 together β€” the OR gates merge 011 and 100 into 111, a code claiming input 7 was pressed. It never was! Priority ON: 4 cleanly wins and the code is honest again. 3. Selection: in MUX/DEMUX mode set D2=1 (others 0), steer S1S0 to 10 β€” the channel goes live and Y2 lights; every other select code sends 0. 4. TDM: set D0=1, D1=0, D2=1, D3=0, enable Auto-Scan, and watch each value pop out of its own output in rotation β€” four signals sharing one wire. 5. The bit budget: in ADC/DAC mode set 1 bit β€” the staircase is a crude two-level caricature. Slide to 6 bits and watch it hug the wave. 6. Sampling matters too: at any resolution, stretch the sample interval and watch detail vanish between samples β€” resolution AND rate together set fidelity.

Key Facts Reference Box

Encoder
Many lines β†’ few coded bits (compress)
Priority Encoder
Highest-priority active input wins + valid flag
Decoder
N-bit code β†’ one of 2α΄Ί lines active
Decoder Enable
EN=0 β†’ all outputs inactive
Multiplexer
Data selector: many in β†’ one out
Demultiplexer
Data distributor: one in β†’ many out
Select Line Rule
n select lines address 2ⁿ channels
Decoder = DEMUX
Add data via enable β†’ same circuit
TDM
Scan select lines β†’ many signals share one channel
ADC Three Steps
Sample β†’ Quantize β†’ Encode
Resolution
n bits = 2ⁿ levels · step = range/2ⁿ
8-bit on 5 V
256 levels β‰ˆ 19.5 mV steps
Sampling Rate
β‰₯ 2Γ— highest signal frequency
DAC
Binary code β†’ proportional analog output
DAC Output
Staircase β†’ low-pass filter smooths it
Classic Chips
74148 encoder Β· 74138 decoder Β· 74151 MUX

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