Latches & Flip-Flops

The SR Latch

The simplest usable bistable adds two control inputs to the cross-coupled core: Set and Reset, with complementary outputs Q and Q̅.

Operation

• Set (S=1, R=0): forces Q = 1. The latch now "remembers" being set even after S returns to 0.
• Reset (R=1, S=0): forces Q = 0.
• Hold (S=0, R=0): neither input asserted — the feedback loop preserves whatever state was last written. This is the memory in action.

Applications

Simple control flags and basic state storage — any circuit that must remember whether a condition has occurred: an over-temperature event latched until an operator clears it, an alarm that stays on after a momentary trigger, or the classic switch debouncer that turns a bouncing mechanical contact into one clean transition.

The Gated SR Latch

A bare SR latch listens to its inputs all the time — any glitch on S or R instantly corrupts the stored bit. The gated (enabled) SR latch fixes that by putting the latch behind a gate: an enable input that opens or closes the door.

Operation

• EN = 1 (door open): the latch responds normally to Set and Reset.
• EN = 0 (door closed): S and R are completely ignored; the latch holds its state no matter what the inputs do.

Construction is two AND gates in front of the SR core: S and R each get ANDed with EN, so with EN=0 the core sees 0,0 — the hold condition — regardless of the actual inputs. Note the invalid state survives: EN=1 with S=R=1 is still forbidden.

Why Gating Matters

This is the first appearance of an idea that dominates the rest of the lesson: controlled updating rather than continuous response. You choose when the storage element is writable. In timing-sensitive control logic, the enable window is opened only when the inputs are known to be valid and quiet.

Applications

Gated storage in timing-sensitive control logic and simple memory gating — e.g., latching a sensor reading only during the interval it's guaranteed stable, or write-protecting a stored flag while other circuitry is switching.

The D Latch — and Its Enable

The gated SR latch still carries the forbidden S=R=1 landmine. The D latch removes it with one elegant move: replace the two inputs with a single Data input, wired to S directly and to R through an inverter. Now S and R are always opposites — the invalid combination is structurally impossible.

Operation

• While enabled, the output is a live window onto the input — wiggle D and Q wiggles in sympathy. This is why it's called the transparent latch.
• The instant EN falls, Q freezes at whatever D held at that moment. The falling edge of enable is effectively the "capture" event.

The D Latch with Explicit Enable

The same concept packaged with explicit level-sensitive write control: if EN = 1, Q tracks D; if EN = 0, Q retains its prior state. This is the form you'll meet as register-like storage, for gating data into subsystems, and on bus interfaces — a latch grabs the data lines during the brief window an address is valid, then holds them for the slower peripheral while the bus moves on.

Applications

Temporary data storage, buffering, and input/output interfacing — anywhere you need to catch a value during a known-valid window and hold it afterward.

Latch vs. Flip-Flop: Level vs. Edge

Everything so far has been level-sensitive. The flip-flop makes one decisive change: it responds not to the level of a control signal but to its transition — the clock edge. On the rising (or falling) edge, the device samples its inputs, updates once, and then ignores everything until the next edge.

Why the Edge Wins in Big Systems

• Predictability: every storage element in the system updates at the same instant. Between edges, all signals are free to ripple through combinational logic — nothing gets stored until the next tick.
• Noise immunity: the vulnerable window shrinks from the whole enable interval to the tiny setup/hold window around the edge. Input glitches at any other time are simply invisible.
• Composability: chain a thousand flip-flops on one clock and the design still behaves — the discipline behind every synchronous processor, FPGA, and memory controller.

Reading the Symbol

The triangle (▷) on the clock pin is the flip-flop's badge: it means "edge-triggered here." A plain triangle means rising-edge; a bubble in front of it means falling-edge. Latch symbols have no triangle — a plain EN pin means level-sensitive.

SR and D Flip-Flops — and the Clock Enable

SR Flip-Flop

The edge-triggered counterpart of the SR latch. On the active clock edge: S=1 drives Q high, R=1 drives Q low, and S=R=0 preserves the current state. Between edges, S and R can do anything without effect. It inherits the SR family curse — S=R=1 at the edge is still undefined — which limits it to control systems where separate, mutually exclusive set and reset commands are guaranteed by design.

D Flip-Flop: The One-Bit Memory Cell

Q takes the value on D at the edge instant, then ignores all later D changes until the next edge. That's the whole device — and that simplicity is why it dominates: it is the classic one-bit memory cell for synchronous systems. Set D early, clock the system, and the value is captured cleanly with no invalid states and no ambiguity.

Applications: registers, shift registers, pipeline stages, counters, and synchronous data transfer — essentially all of modern digital design's storage is D flip-flops in bulk.

D Flip-Flop with Enable (Clock Enable)

Adds a conditional-load input: EN=1 → load new data on the edge; EN=0 → hold the old value even though the clock keeps running. This is the standard way to make storage conditional without touching the clock wiring — gating the clock itself invites glitches and timing skew, while a clock enable keeps the clean global clock and simply tells the flip-flop "skip this one."

Applications: register files (only the addressed register loads), state retention, and controlled pipeline updates (stalling a stage without stopping the clock).

The JK Flip-Flop: The Universal One

The JK is the SR flip-flop with its one flaw engineered away. Internal feedback from Q and Q̅ steers the inputs so that the formerly forbidden both-asserted case becomes something useful: toggle.

Operation (at each active clock edge)

Why "Universal"

The JK can impersonate every other flip-flop, which is why it earned the name universal flip-flop:

• As a D flip-flop: drive K with the inverse of J (K = J̅) — now J acts exactly like a D input.
• As a T flip-flop: tie J and K together — the shared input becomes T (0 = hold, 1 = toggle).
• As an SR flip-flop: use J as Set and K as Reset, with the bonus that the "both asserted" case is now defined and safe.

Applications: counters (the toggle mode is precisely what binary counting needs), toggle circuits, and flexible sequential logic design where one part number must cover many roles — the reason classic TTL families led with the 7476 dual JK.

The T Flip-Flop and Frequency Division

Strip the JK down to its most celebrated trick and you get the T (toggle) flip-flop — a single input device:

The Divide-by-2 Miracle

With T=1, Q inverts on every active edge. Follow the arithmetic: the clock must rise twice for Q to complete one full 0→1→0 cycle. Therefore:

• One stage: 1 MHz in → 500 kHz out, a perfect 50% duty-cycle square wave regardless of the input's duty cycle.
• Chain of stages (each Q clocking the next stage): ÷2, ÷4, ÷8, ÷16 … Read the chain's outputs together and they count in binary — a ripple counter is nothing but T flip-flops holding hands.
• Fifteen stages: 32,768 Hz ÷ 2¹⁵ = exactly 1 Hz — which is literally how a quartz watch turns its crystal into seconds.

Applications: binary counters, frequency division, clock prescalers, and simple state toggling (a push-on/push-off power button is one T flip-flop).

Operations Vocabulary & Where These Devices Live

The Five Operations — Precise Definitions

The Application Map