โšก ELT 102 ยท Digital Logic & Solid State Devices Lesson 8 of 8
Unit 3 ยท Digital Foundations ยท Capstone

Oscillators, Timers & Counters

The circuits that give digital systems a heartbeat and a memory of time: oscillators generate the clock, timers shape precise intervals, and counters โ€” built from Lesson 6's flip-flops โ€” count edges into binary, BCD, up/down, and Johnson sequences.

โฑ 3 Hours Study ๐Ÿ“‹ 9 Core Topics ๐Ÿ“ Symbol Library (6 circuits) ๐Ÿ“ˆ 555 Timer Scope + 4-Counter Lab

Learning Objectives

By the end of this lesson, you will be able to:

  • Explain how an oscillator sustains a repeating waveform without an input signal, and distinguish RC relaxation oscillators from crystal oscillators by stability and application.
  • Analyze 555 timer astable operation โ€” the capacitor cycling between โ…“ and โ…” VCC โ€” and calculate frequency with f = 1.44 / ((Rโ‚+2Rโ‚‚)C).
  • Calculate monostable (one-shot) pulse width using T = 1.1ยทRยทC and identify applications for triggered timing pulses.
  • Describe how a quartz crystal plus a flip-flop divider chain produces precision clocks, from wristwatches to microprocessors.
  • Distinguish asynchronous (ripple) counters from synchronous counters, and explain modulus as the number of states a counter cycles through.
  • Trace a 4-bit binary counter through its 16 states, reading each output as a divide-by-2โฟ frequency divider.
  • Explain how a BCD (decade) counter resets at ten, and how cascaded decades drive multi-digit displays through Lesson 7's decoders.
  • Analyze up/down counter direction control and Johnson (twisted-ring) counter operation, including its 2n-state sequence and glitch-free decoding.
  • Verify every circuit hands-on in the embedded 555 Timer Scope and Counter Lab, connecting oscillator โ†’ clock โ†’ counter into one working timing chain.

Key Terms & Concepts

Click any card to reveal its definition.

Oscillators
Oscillator
Oscillators
๐Ÿ”„ Click to reveal definition
Definition
A circuit that generates a repeating waveform with no input signal โ€” positive feedback plus a timing element sustains the oscillation. Every clocked system in Lessons 6โ€“7 assumed one exists; this lesson builds it.
Astable Operation
Oscillators
๐Ÿ”„ Click to reveal definition
Definition
"No stable state": the output continuously flips between HIGH and LOW on its own. Contrast with Lesson 6's bistable (two stable states) and the timer's monostable (one stable state) โ€” the three siblings of multivibrator circuits.
Relaxation Oscillator
Oscillators
๐Ÿ”„ Click to reveal definition
Definition
An oscillator that charges a capacitor toward one threshold, snaps, discharges toward another, snaps back โ€” over and over. The 555 astable is the classic example: RC charging (Lesson 2's time constants) plus comparator thresholds (Lesson 4).
Crystal Oscillator
Oscillators
๐Ÿ”„ Click to reveal definition
Definition
An oscillator disciplined by a quartz crystal's mechanical resonance โ€” stable to parts per million, versus a few percent for RC circuits. The 32.768 kHz watch crystal and every microprocessor clock source belong to this family.
Period & Frequency
Oscillators
๐Ÿ”„ Click to reveal definition
Definition
Period T is the time of one complete cycle; frequency f = 1/T is cycles per second (Hz). A 1 kHz clock has a 1 ms period. The two are one fact wearing two units.
Duty Cycle
Oscillators
๐Ÿ”„ Click to reveal definition
Definition
The percentage of each period the output spends HIGH. A perfect square wave is 50%. The basic 555 astable always exceeds 50% because the capacitor charges through two resistors but discharges through one.
Timers
555 Timer
Timers
๐Ÿ”„ Click to reveal definition
Definition
The most-manufactured IC in history โ€” two comparators, a resistor divider setting โ…“ and โ…” VCC thresholds, an SR latch (Lesson 6!), and a discharge transistor. Wire it two ways and it's an oscillator or a precision one-shot.
Monostable (One-Shot)
Timers
๐Ÿ”„ Click to reveal definition
Definition
One stable state: the output rests LOW until triggered, produces exactly one pulse of width T = 1.1ยทRยทC, then returns to rest. Used for debounce delays, precise strobe pulses, and timeout intervals.
Threshold & Trigger
Timers
๐Ÿ”„ Click to reveal definition
Definition
The 555's two comparator inputs: Trigger fires the internal latch when the capacitor falls below โ…“ VCC; Threshold resets it when the capacitor rises above โ…” VCC. The sawtooth bouncing between them is visible live in the Lab.
RC Time Constant (ฯ„)
Timers
๐Ÿ”„ Click to reveal definition
Definition
ฯ„ = RยทC, the natural clock of every timing circuit: a capacitor charges to ~63% of its target in one ฯ„. All 555 math is disguised time constants โ€” bigger R or C, slower everything, in exact proportion.
Counters
Counter
Counters
๐Ÿ”„ Click to reveal definition
Definition
A register of flip-flops that steps through a fixed sequence of states, one step per clock edge. Lesson 6's toggle behavior, organized: the outputs read as a number that increments with every pulse counted.
Modulus (MOD)
Counters
๐Ÿ”„ Click to reveal definition
Definition
The number of unique states a counter cycles through before repeating. Four flip-flops give up to MOD-16 (0โ€“15); a decade counter is MOD-10; a 4-bit Johnson counter is MOD-8. Modulus also equals the frequency division ratio.
Ripple (Asynchronous) Counter
Counters
๐Ÿ”„ Click to reveal definition
Definition
Each flip-flop is clocked by the previous stage's output โ€” the count "ripples" down the chain. Minimal wiring, but stage delays accumulate, so high-speed or glitch-sensitive designs use synchronous counters instead.
Synchronous Counter
Counters
๐Ÿ”„ Click to reveal definition
Definition
Every flip-flop shares the same clock; gate logic decides which stages toggle each edge. All outputs change together โ€” no ripple delay, no decoding glitches. The 74163 is the classic packaged example.
BCD (Decade) Counter
Counters
๐Ÿ”„ Click to reveal definition
Definition
A MOD-10 counter: counts 0โ€“9, then reset logic detects state 1010โ‚‚ and forces a return to 0000. One decade per decimal digit โ€” cascade them and feed Lesson 7's BCD-to-seven-segment decoders to build any numeric display.
Up/Down Counter
Counters
๐Ÿ”„ Click to reveal definition
Definition
A counter with a direction control: count up on one setting, down on the other (some versions use separate up/down clock inputs). The natural fit wherever a quantity both rises and falls โ€” position, inventory, people in a room.
Johnson (Twisted-Ring) Counter
Counters
๐Ÿ”„ Click to reveal definition
Definition
A shift register whose inverted last output feeds back to its input. n flip-flops give 2n states (4 FFs โ†’ 8 states) in a walking-bit pattern where only one bit changes per clock โ€” so decoded outputs are glitch-free.
Terminal Count / Carry Out
Counters
๐Ÿ”„ Click to reveal definition
Definition
The output that pulses when a counter reaches its final state (15 for MOD-16, 9 for a decade). It clocks the next counter in a cascade โ€” how single digits become odometers, frequency counters, and digital clocks.

๐Ÿ“ Circuit Symbol & Diagram Library

The timing family at a glance: the 555 in its two personalities, the quartz crystal's distinctive symbol, and the three counter architectures โ€” read where the clock enters (rippling stage-to-stage versus shared by all) and where the feedback goes (Johnson's twist) to identify each on sight.

555 OUT R1R2C
555 Astable
Free-running oscillator ยท C bounces between โ…“ and โ…” VCC
f = 1.44 / ((Rโ‚+2Rโ‚‚)ยทC)
Duty(Rโ‚+Rโ‚‚)/(Rโ‚+2Rโ‚‚)
Always> 50% HIGH
555 TRIG โท one pulse T = 1.1ยทRยทC
555 Monostable
One-shot: trigger in โ†’ single clean pulse out, then back to rest
RยทCPulse T
10kฮฉยท10ยตF0.11 s
100kฮฉยท100ยตF11 s
XTAL 32.768 kHz รท2 โ€ฆ15 15 T flip-flops โ†’ 1 Hz
Crystal + Divider Chain
Quartz precision รท 2ยนโต = one perfect second (Lesson 6's T FFs)
SourceStability
RC (555)~few %
Crystalparts per million
Q0Q1Q2Q3 CLK each Q clocks the next stage
Ripple Counter (4-bit)
Asynchronous: count ripples down the chain ยท Q0=รท2 โ€ฆ Q3=รท16
FFsMODCounts
4160โ€“15
ENCLK Q0-Q3 CTR รท16 + carry out (TC)
Synchronous Counter
One shared clock, all outputs change together ยท 74163 class
TypeDelay
Rippleaccumulates
Syncone FF delay
Q0Q1Q2Q3 Q̅3 feeds back to input โ€” the "twist"
Johnson (Twisted-Ring)
Shift register + inverted feedback ยท 2n states, one bit changes per clock
4 FFsSequence
0000โ†’0001โ†’0011โ†’0111โ†’1111โ†’1110โ†’1100โ†’1000โ†’โ€ฆ

Core Lesson Content

Giving Digital Systems a Heartbeat

Lessons 6 and 7 kept saying "on the clock edge" โ€” but where do clock edges come from? This capstone lesson completes the picture with the timing chain every digital system contains:

  1. Oscillators generate the repeating waveform โ€” the raw heartbeat โ€” with no input signal at all.
  2. Timers shape precise intervals from that behavior: a pulse exactly this wide, a delay exactly that long.
  3. Counters โ€” flip-flops from Lesson 6, organized โ€” count the edges into numbers, divide frequencies, and sequence events.
Oscillator โ†’ clock edges โ†’ counters count them โ†’ decoders (L7) display them
A digital clock, a frequency counter, and a stopwatch are all this one chain.
๐Ÿ’ก The Whole Course in One Circuit
A 555 timer is a resistor-capacitor charging circuit (Lesson 2's time constants), watched by two comparators (Lesson 4), driving an SR latch (Lesson 6), whose output clocks counters (this lesson) that feed display decoders (Lesson 7). Every device on the chip's die is something you've already mastered โ€” this lesson just connects them into time.

Try It Live

Oscillators: Output Without Input

Every amplifier in Lesson 4 needed an input signal. An oscillator needs none โ€” it manufactures its own repeating waveform from two ingredients:

  • Positive feedback: a portion of the output returned in-phase to the input, reinforcing any change until the circuit swings rail to rail (the same positive feedback that made Lesson 4's Schmitt trigger snap).
  • A timing element: something that delays the swing-back โ€” an RC network, an LC tank, or a quartz crystal โ€” setting the period of the resulting oscillation.

The Relaxation Oscillator

The workhorse pattern for digital clocks: a capacitor charges toward a threshold, a comparator snaps the output, the capacitor discharges toward a second threshold, and the comparator snaps back. Charge, snap, discharge, snap โ€” forever. The output is a square wave (perfect for clocking logic) and the capacitor voltage is a sawtooth bouncing between the two thresholds โ€” both waveforms are drawn live in the Lab's 555 mode.

The Multivibrator Family

CircuitStable StatesBehaviorYou Met It In
BistableTwoHolds either state until commanded โ€” a latch/flip-flopLesson 6
MonostableOneRests until triggered, emits one timed pulse, returns to restTab 4
AstableNoneFlips continuously on its own โ€” an oscillatorTab 3
๐ŸŽฏ Quiz Tip
"How many stable states?" is the classifier: bi = 2, mono = 1, a = none. The prefix answers the exam question by itself.

The 555 Timer in Astable Mode

The 555 โ€” billions manufactured yearly since 1972 โ€” packages the relaxation oscillator into eight pins. Inside: a resistor divider creating โ…“ and โ…” VCC reference points, two comparators watching them, an SR latch, and a discharge transistor. In astable wiring, external parts Rโ‚, Rโ‚‚, and C set the tempo:

  1. C charges toward VCC through Rโ‚ + Rโ‚‚; output is HIGH.
  2. C reaches โ…” VCC โ†’ threshold comparator resets the latch โ†’ output LOW, discharge transistor opens a path.
  3. C discharges through Rโ‚‚ only toward ground.
  4. C falls to โ…“ VCC โ†’ trigger comparator sets the latch โ†’ output HIGH โ€” back to step 1, forever.
f = 1.44 / ((Rโ‚ + 2Rโ‚‚)ยทC)   ยท   Duty = (Rโ‚+Rโ‚‚)/(Rโ‚+2Rโ‚‚)
Example: Rโ‚=10 kฮฉ, Rโ‚‚=47 kฮฉ, C=10 ยตF โ†’ f = 1.44/(104k ร— 10ยต) โ‰ˆ 1.4 Hz, duty โ‰ˆ 55%
โš ๏ธ Watch Out: Duty Cycle Is Always Above 50%
Charging runs through two resistors, discharging through one โ€” so HIGH time always exceeds LOW time in the basic circuit. Need a true 50% square wave? Make Rโ‚‚ โ‰ซ Rโ‚ (approaches 50%), add a diode across Rโ‚‚, or simply divide the output by 2 with a T flip-flop โ€” Lesson 6's trick, which delivers a perfect 50% regardless.

Applications

LED flashers and tone generators, clock sources for counters where a few percent of drift is fine, PWM foundations, and โ€” historically โ€” half the hobby-electronics projects ever published.

The 555 Timer in Monostable Mode: The One-Shot

Rewire the same chip and it becomes a precision pulse-maker with one stable state: output LOW, capacitor held empty. Then:

  1. A falling edge on the trigger input (below โ…“ VCC) sets the latch โ€” output snaps HIGH.
  2. C charges through R toward VCC.
  3. When C reaches โ…” VCC, the threshold comparator resets the latch โ€” output returns LOW and C is discharged, ready for the next trigger.
Pulse width:  T = 1.1 ยท R ยท C   (time to charge from 0 to โ…” VCC โ‰ˆ 1.1 time constants)
Example: R = 100 kฮฉ, C = 10 ยตF โ†’ T = 1.1 ร— 1.0 s = 1.1 seconds โ€” regardless of how long the trigger lasts

That last clause is the magic: a sloppy, bouncing, variable-length input produces one clean, exactly-timed output pulse. The one-shot is a pulse standardizer.

Applications

  • Switch debouncing: a bouncing pushbutton (dozens of edges) becomes one clean pulse โ€” solving the very problem Lesson 6's SR latch debouncer addressed, with adjustable timing.
  • Timed intervals: darkroom timers, delay-off lighting, watchdog timeouts, missing-pulse detectors.
  • Pulse-width standardization ahead of counters โ€” guaranteeing every counted event has identical width.
๐ŸŽฏ Quiz Tip
Two formulas carry this chip: astable f = 1.44/((Rโ‚+2Rโ‚‚)C), monostable T = 1.1RC. Anchor them by remembering which mode has two resistors โ€” the oscillator charges through two, the one-shot through one.

Crystal Oscillators and System Clocks

RC oscillators drift โ€” resistor tolerance, capacitor aging, and temperature swing the 555's frequency by a few percent. Fine for a blinking LED; catastrophic for a watch (a 1% error is ~14 minutes per day). Precision timing uses quartz:

  • The piezoelectric bargain: squeeze quartz and it makes a voltage; apply a voltage and it flexes. Cut a crystal to size and it rings at one mechanical resonant frequency with extraordinary purity โ€” an electrically-accessible tuning fork.
  • In the feedback loop: replace the RC timing network with the crystal and the oscillator locks to the crystal's resonance โ€” stable to parts per million (seconds per month, not minutes per day).
  • The magic number 32,768: watch crystals are cut for 32,768 Hz = 2ยนโต Hz, so a chain of fifteen T flip-flops (Lesson 6's divide-by-2, fifteen times) delivers exactly 1 Hz. Every quartz watch on Earth is this circuit.
32,768 Hz โ†’ รท2ยนโต (fifteen toggle stages) โ†’ 1.000 Hz โ†’ drives the seconds counter

Clock Distribution in Real Systems

A microprocessor board typically runs one crystal oscillator, then uses dividers (counters!) and multipliers to derive every internal clock โ€” CPU, memory, peripherals โ€” from that single disciplined source. When a technician sees timing chaos across a whole board, the crystal and its oscillator circuit are the first suspects: one part, every symptom.

๐Ÿ’ก Design Trade Summary
555/RC: cheap, adjustable, drifty โ€” use where "about right" is right. Crystal: fixed-frequency, ppm-stable โ€” use wherever time is money, data, or law (clocks, communications, instrumentation).

Counter Fundamentals

A counter is Lesson 6's payoff: flip-flops arranged so their collective state steps through a fixed sequence, one step per clock edge. Read the outputs as a binary number (Lesson 5) and the circuit literally counts the pulses it has received.

Modulus: A Counter's Size

MOD = number of unique states before the sequence repeats
n flip-flops โ†’ up to 2โฟ states  ยท  4 FFs โ†’ MOD-16 (counts 0โ€“15)  ยท  MOD also = frequency division ratio

Asynchronous (Ripple) vs. Synchronous

FeatureRipple (Asynchronous)Synchronous
ClockingOnly stage 0 gets the clock; each Q clocks the next stageEvery flip-flop shares the same clock
WiringMinimal โ€” T flip-flops holding handsExtra gating decides which stages toggle
Speed/glitchesDelays accumulate down the chain; outputs change at slightly different times (decoding glitches)All outputs change together โ€” one flip-flop delay total
UseFrequency division, slow counting, minimal partsHigh-speed counting, decoded outputs, packaged MSI counters (74163)

The ripple counter's charm is its honesty: it's nothing but the T flip-flop divide-by-2 from Lesson 6, chained. Q0 toggles every clock (รท2), Q1 toggles every Q0 cycle (รท4), Q2 (รท8), Q3 (รท16) โ€” and read together, Q3Q2Q1Q0 is the count in binary. Counting and frequency division are the same circuit viewed two ways.

๐ŸŽฏ See Both Views at Once
In the Lab's Counter mode, the LED row shows the number view while the timing lanes below show the divider view โ€” same flip-flops, same instant. Count the CLK-lane edges between Q3 edges: sixteen.

The 4-Bit Binary Counter and the BCD (Decade) Counter

4-Bit Binary: MOD-16

Four flip-flops count 0000 through 1111 โ€” decimal 0 to 15 โ€” then roll over to 0000 and raise a terminal count / carry out pulse. That carry clocks the next 4-bit counter in a cascade, exactly as a car odometer's units wheel nudges the tens wheel. Applications: event counting, address generation, timers, and รท16 prescalers.

BCD (Decade): MOD-10

Humans read decimal, so display systems count in binary-coded decimal: each digit gets its own MOD-10 counter that counts 0โ€“9 and resets. The construction trick:

Count normally 0000โ†’1001 (0โ€“9). The moment state 1010โ‚‚ (10) appears,
a NAND gate watching Q3ยทQ1 fires the asynchronous CLEAR โ†’ counter snaps to 0000.
  • The reset is Lesson 5 logic: 1010 is the first state where Q3 AND Q1 are both high โ€” two gate inputs detect it. The illegal state exists for only nanoseconds.
  • Cascading decades: each counter's rollover clocks the next digit. Three decades + three of Lesson 7's BCD-to-seven-segment decoders = a 0โ€“999 display. This is the anatomy of every digital multimeter, frequency counter, and scoreboard.
  • Division by ten: a decade counter is also a รท10 prescaler โ€” chain them for รท100, รท1000 in instrumentation.
๐Ÿ’ก Watch the Reset Happen
In the Lab, select BCD and single-step the clock past 9. The count snaps to 0 โ€” and the decimal readout confirms the counter never displays 10 through 15. Compare against Binary mode, which sails on to 15 before rolling over.

The Up/Down Counter

Some quantities only grow โ€” elapsed seconds, total visitors. Others rise and fall โ€” items in stock, position on a track, people in a room. The up/down counter serves the second kind with a direction control:

  • Direction input: one control line selects the sequence โ€” UP counts 0,1,2,โ€ฆ,15,0 while DOWN counts 15,14,โ€ฆ,0,15. Internally, gating chooses whether each stage watches the previous stage's Q (up) or Q̅ (down).
  • Dual-clock versions: some parts (the classic 74193) instead provide separate count-up and count-down clock inputs โ€” pulse whichever event occurred.
  • Borrow and carry: full up/down parts provide both a carry (rolled over the top) and a borrow (rolled under zero) for cascading in either direction.

Applications

  • Position tracking: a motor encoder pulses up for one direction of rotation, down for the other โ€” the count is the position. CNC machines and 3D printers live on this.
  • Inventory and occupancy: entry sensor counts up, exit sensor counts down โ€” parking garages ("SPACES: 47") and room-occupancy limits.
  • Elevator floor indicators, kitchen-timer countdowns, and any set-then-count-to-zero interval logic.
๐ŸŽฏ Lab Check
In Counter mode, select Up/Down, count up to 5, flip the direction button, and step again: 4, 3, 2โ€ฆ Watch the timing lanes reverse their pattern โ€” Q0 still toggles every edge, but the higher bits now step down through the codes.

The Johnson (Twisted-Ring) Counter โ€” and the Family Portrait

Construction: One Twist

Take Lesson 6's shift register and close the loop โ€” feed the last output back to the input and data circulates in a ring. Now add the twist: feed back the inverted last output (Q̅โ‚ƒ โ†’ Dโ‚€). That single inversion creates the Johnson counter:

4 flip-flops, sequence (Q3Q2Q1Q0): 0000 โ†’ 0001 โ†’ 0011 โ†’ 0111 โ†’ 1111 โ†’ 1110 โ†’ 1100 โ†’ 1000 โ†’ 0000 โ€ฆ
A wave of 1s washes in, then washes out โ€” 2n states from n flip-flops (here MOD-8)

Why Designers Love It

  • Only one bit changes per clock. Decode any state with a single 2-input AND gate, and the decoded outputs are glitch-free โ€” no ripple-counter race conditions, no momentary false states.
  • 2n states beats the plain ring counter's n states for the same hardware (a 4-FF ring gives only 4 states; the twist doubles it).
  • Self-clocking sequencing: the overlapping waveforms are naturally phase-shifted square waves โ€” historically used for quadrature signals and switch-tail sequencers.

Applications: state sequencers and phase generators (stepper-motor drive waveforms), the classic 4017-style LED chasers (a Johnson counter plus decoding), and glitch-free timing-signal generation.

The Counter Family, Side by Side

CounterMOD (4 FFs)Sequence StyleSignature Application
4-bit binary16Binary count 0โ€“15Event counting, รท16, addressing
BCD (decade)100โ€“9, reset at 1010Digit displays, รท10 prescalers
Up/Down16 (both ways)Direction-controlledPosition, inventory, occupancy
Johnson8 (= 2n)Walking-1s wave, one bit changes per clockGlitch-free sequencing, phase generation
๐Ÿ’ก Course Complete: The Full Signal Chain
Semiconductors steered current (L1), supplies powered it (L2), transistors switched it (L3), op-amps refined it (L4), gates computed with it (L5), flip-flops remembered it (L6), routers and converters moved it (L7) โ€” and now oscillators, timers, and counters give it time. From a doped silicon crystal to a working digital clock: that's ELT 102.

๐Ÿ“ˆ Timing & Counting Lab

Two instruments, one timing chain. 555 Timer mode: a live scope showing the capacitor voltage sawing between the โ…“ and โ…” VCC thresholds while the output squares off above it โ€” drag Rโ‚, Rโ‚‚, and C and verify the frequency formula in real time, or switch to monostable and fire single pulses. Counter mode: all four counters from this lesson โ€” 4-bit binary, BCD, up/down, and Johnson โ€” with an LED state row, decimal readout, and the scrolling timing lanes that reveal frequency division as it happens.

Auto-clock (free-running)
๐Ÿ’ก Guided Explorations
1. Verify the formula: 555 astable, Rโ‚=10k, Rโ‚‚=47k, C=10ยตF โ€” the readout should confirm โ‰ˆ1.4 Hz. Halve C and watch frequency double: pure proportionality. 2. The duty-cycle law: make Rโ‚ huge and Rโ‚‚ tiny โ€” duty approaches 100%; reverse them โ€” it approaches (but never reaches) 50%. 3. One clean pulse: switch to Monostable and fire the trigger repeatedly โ€” every pulse is identical width T = 1.1ยทRโ‚ยทC no matter how you mash the button. 4. Two views of one circuit: Counter mode, 4-bit binary, auto-clock โ€” read the LED row as a number while the lanes below show Q0โ€“Q3 dividing by 2, 4, 8, 16. 5. The decade reset: BCD mode, single-step past 9 โ€” it snaps to 0, never showing 10โ€“15. 6. Reversal: Up/Down โ€” count to 5, flip DIR, and watch the lanes' pattern mirror. 7. The wave: Johnson mode, auto-clock โ€” a wave of 1s washes across the LEDs and back, one bit changing per clock: 8 states from 4 flip-flops, glitch-free by construction.

Key Facts Reference Box

Oscillator Recipe
Positive feedback + timing element
Multivibrator Family
Bistable 2 states ยท Mono 1 ยท Astable 0
555 Thresholds
Trigger at โ…“ VCC ยท Threshold at โ…” VCC
555 Astable Frequency
f = 1.44 / ((Rโ‚+2Rโ‚‚)ยทC)
555 Astable Duty
(Rโ‚+Rโ‚‚)/(Rโ‚+2Rโ‚‚) โ€” always > 50%
555 Monostable Pulse
T = 1.1 ยท R ยท C
RC vs Crystal Stability
Few % vs parts per million
Watch Crystal
32,768 Hz = 2ยนโต โ†’ รท2ยนโต = 1 Hz
Modulus
States before repeat = division ratio
n Flip-Flops
Up to 2โฟ states (4 FFs โ†’ MOD-16)
Ripple vs Synchronous
Chained clocks vs one shared clock
4-Bit Binary Counter
0โ€“15 ยท Q0..Q3 = รท2, รท4, รท8, รท16
BCD Counter
0โ€“9, NAND detects 1010 โ†’ reset
Up/Down Counter
Direction control ยท position & inventory
Johnson Counter
Inverted feedback ยท 2n states ยท 1 bit/clock
Cascading
Carry out clocks the next digit/stage

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โ† Lesson 7: Encoders, Decoders & Converters ๐Ÿ Course Complete โ€” ELT 102 Home