The Heartbeat: Timers, Oscillators & the Johnson Counter

Learning Objectives

Key Terms & Concepts

🖥 Tinkercad Setup Notes: Your Own Clock at Last

Ninth lab, and a milestone: the function generator stays in the drawer. Everything that ticks in this lab ticks because you built the tick:

• Tinkercad HAS the 555 — search "555" in the components panel (it appears as "Timer"). 8-pin DIP: 1 GND, 2 TRIG, 3 OUT, 4 RESET, 5 CTRL, 6 THRES, 7 DISCH, 8 V_CC. Hover pins to confirm; the notch/dot ritual applies as ever. Its output can source an LED directly (through 220 Ω) and clock your counters at the same time.
• Tinkercad LACKS the CD4017 (the Johnson-counter-with-decoder chip) — so Part 5 builds the Johnson architecture honestly from two 74HC74s, and the 4017 is documented in the reference table as the commercial one-chip version. By now you know the pattern: the missing chip is the better lesson.
• Capacitors: use the polarized capacitor for 10 µF (mind the + terminal — it faces the charging side, away from GND) and set values by clicking: 10 µF and 1 µF are the two you need. Tinkercad simulates RC charging faithfully, so your scope will show the real exponentials.
• Scope technique for this lab: two oscilloscopes — one on the 555 output (pin 3), one on the capacitor (pins 2/6) — turn the ⅓–⅔ shuttle into something you can watch. Set ~500 ms/div for the 1 Hz clock. The capacitor trace is the soul of the chip; don't skip it.
• Clock routing with pull-ups (Part 4): when a slide switch routes your clock to the '193's UP or DOWN pin, the unselected pin must not float — give each clock pin its own 10 kΩ pull-up to +5 V, and let the switch pull the chosen pin to the 555's output. The '193's three tie-downs from the Counters lab still apply: CLR (14) LOW, LOAD̄ (11) HIGH.
• Johnson wiring discipline: the twisted ring is four wires plus one twist, but on two chips the geometry gets confusing. Label columns Q1–Q4, wire the bucket brigade first (Q1→D2, Q2→D3, Q3→D4), the twist last (Q̄4→D1), and route one clock line to all four CLK pins — the Johnson counter is synchronous by construction.

🔧 Virtual Parts List

📐 The Circuits You Will Build

Four figures: the oscillator, the one-shot, the self-clocked counter system, and the twisted ring. The first two share every pin habit; spot the single wiring difference that changes the chip's personality.

Reference: Timing & Ring Cheat Sheet

🛠 Step-by-Step Procedure

Session 1 = Parts 1–3 (oscillator, one-shot, self-clocked counter). Session 2 = Parts 4–5 (direction control, Johnson ring) + analysis. Predict before you measure, every time.

Part 1 — The Astable Oscillator: Build Your Clock (≈30 min)

1. Workspace. New circuit "LastName – Timer Lab." Breadboard, 5.00 V to rails. Seat the 555 across the trench (notch ritual — pin 1 lower-left).
2. Power and the two killer pins. Pin 8 → +5 V, pin 1 → GND, and immediately: pin 4 (RESET) → +5 V. Add the traditional 0.01 µF from pin 5 → GND.
3. Timing network per Figure 1: R_A = 10 kΩ from +5 V to pin 7; R_B = 68 kΩ from pin 7 to pin 6; C = 10 µF (polarized — + terminal to pin 6 side) from pin 6 to GND; and the jumper that makes it oscillate: pin 2 → pin 6.
4. Predict first. In Data Table 1, compute f = 1.44/((R_A+2R_B)·C) and duty = (R_A+R_B)/(R_A+2R_B) for these values before simulating. (You should get ≈ 0.99 Hz and ≈ 53%.)
5. Beacon and scopes. LED + 220 Ω from pin 3 (OUT) to GND. Oscilloscope #1 on OUT; oscilloscope #2 on the capacitor (pin 6). 500 ms/div. Start the simulation: the LED blinks about once per second — your clock is alive.
6. Read the soul of the chip. On scope #2, watch the capacitor shuttle: an exponential climb, a turn, an exponential fall — bouncing between two invisible walls. Measure the turning-point voltages with the multimeter or scope cursors and record them: ≈ 3.33 V and ≈ 1.67 V — the ⅔ and ⅓ thresholds, live. Measure period and duty on scope #1 and complete Data Table 1's first row.
7. Experiment: resistors. Swap to the fast set (R_A = 1 kΩ, R_B = 10 kΩ): predict, measure, record (≈ 6.9 Hz). Notice duty barely moved — why? (Both charge and discharge scaled together.)
8. Experiment: the capacitor decade. Restore 10 k/68 k, swap C to 1 µF: the frequency jumps ×10 (≈ 9.9 Hz). One component, one decade — f ∝ 1/C. Record, then restore C = 10 µF: the ≈1 Hz clock is your lab-wide timebase from here on.

Part 2 — The Monostable One-Shot (≈20 min)

1. Rewire, don't rebuild. Three changes turn Figure 1 into Figure 2: remove R_B and instead join pins 6 and 7; make the timing resistor R = 100 kΩ from +5 V to that junction (C = 10 µF stays from pin 6 to GND); and free pin 2 from pin 6 — it now gets a 10 kΩ pull-up to +5 V and a pushbutton to GND.
2. Predict. T = 1.1·R·C = 1.1 × 100 k × 10 µF = 1.1 s. Write it in Data Table 2 first.
3. Fire the one-shot. Tap the button: the LED lights for just over a second and extinguishes itself. Time it on the scope (or count the blink). Tap again — same pulse, every time.
4. The defining test. Hold the button for a quick tap vs. a slow half-second press: the pulse width doesn't change — the RC network, not your finger, owns the timing. (Caveat to observe: hold the button longer than 1.1 s and the output stays HIGH until you release — pin 2 is level-sensitive. Note it; it's the difference between "one-shot" and "retriggerable" behavior in datasheets.)
5. Timing experiments. Swap R to 47 kΩ (predict ≈ 0.52 s) and 220 kΩ (predict ≈ 2.4 s); measure and record both. You've built an adjustable timer — the circuit inside toasters, delay relays, and watchdog windows.
6. Restore the astable (Figure 1, 10 k/68 k/10 µF) before moving on — Parts 3–5 need the clock.

Part 3 — The Self-Clocked 4-Bit Counter (≈15 min)

1. Seat the '193 with its Counters-lab tie-downs: 16 → +5 V, 8 → GND, CLR (14) → GND, LOAD̄ (11) → +5 V, DOWN clk (4) → +5 V, data inputs grounded. Four LEDs on Q_D Q_C Q_B Q_A (pins 7, 6, 2, 3), MSB left.
2. The historic wire. 555 pin 3 → '193 UP clk (pin 5). For the first time in nine labs, a circuit of yours is clocking a circuit of yours. Run it: the LEDs count 0–15 at your oscillator's pace.
3. Measure the division. Scope CH1 on the 555 OUT, CH2 on Q_D: sixteen clock cycles per Q_D cycle. With the ≈1 Hz clock, Q_D's period is ≈16 s. Record both frequencies in Data Table 3 and verify f/16. Then re-derive the whole chain on paper: f at Q_A, Q_B, Q_C, Q_D.

Part 4 — Direction Control: Up/Down with a Routed Clock (≈15 min)

1. Install the router per Figure 3: two 10 kΩ pull-ups from +5 V to '193 pins 5 and 4 (replacing pin 4's hard tie); slide switch common → 555 OUT, one throw → pin 5, other throw → pin 4.
2. Verify both directions. Switch toward UP: count ascends. Flip to DOWN mid-run: on the very next pulse the count descends from wherever it was. Record a short observed sequence either side of a flip in Data Table 3.
3. Why the pull-ups matter. Temporarily remove pin 4's pull-up (leave it floating) with the switch on UP, and watch for miscounts; restore it. One sentence for the report: what rule from the Counters lab did the pull-ups automate?
4. Application sentence. The parking-garage tally, the volume knob's position, a bidirectional conveyor's item count — name the events that would replace your slide switch in one of them.

Part 5 — The Johnson Twisted Ring (≈35 min)

1. Seat two 74HC74s (power ritual on both). Tie all four PRE̅ pins → +5 V. Tie all four CLR̄ pins together to one column with a 10 kΩ pull-up to +5 V and a pushbutton to GND — this is the ring's reset.
2. Label, then wire the brigade. Name the stages FF1 (chip 1 pins 1–6), FF2 (chip 1 pins 8–13), FF3 (chip 2 pins 1–6), FF4 (chip 2 pins 8–13). Bucket brigade: Q1 (5) → D2 (12) · Q2 (9) → D3 (chip 2 pin 2) · Q3 (chip 2 pin 5) → D4 (chip 2 pin 12).
3. Add the twist. Q̄4 (chip 2 pin 8) → D1 (chip 1 pin 2) — the one inverted wire that makes it a Johnson counter.
4. One clock for all. Run the 555 output to all four CLK pins (chip 1 pins 3 and 11; chip 2 pins 3 and 11). Four LEDs on Q1–Q4, in order left to right.
5. Reset and run. Press the reset button (all LEDs off — state 0000), release, and watch: a wave of light fills the row LED by LED, then a wave of darkness follows it. Record the full sequence — all 8 states, one clock each — in Data Table 4.
6. Verify the defining property. In the table's last column, mark how many bits changed between each pair of consecutive states. The answer is 1, every single time — including the wrap 0001 → 0000. Compare with the binary counter's 0111 → 1000 (four bits at once) and write one sentence on why decoder circuits prefer the Johnson sequence.
7. Decode a state, glitch-free. Seat the 74HC08 and wire one AND: Q1 · Q̄2 → LED (Q̄2 is chip 1 pin 8). Run: the LED fires during exactly one state per cycle — 1000 — a one-per-revolution timing pulse from a 2-input gate. (For contrast: uniquely decoding a binary counter's state 8 needs all four bits.)
8. Visit the parallel orbit. Stop the clock (pull the CLK line off momentarily), and use FF2's PRE̅ (chip 1 pin 10): tap it to GND to force state 0100 — an illegal state. Restore the clock and record the sequence that follows: the ring circulates wrong patterns (0100 → 1010 → 1101 → …) and never returns to the main sequence on its own. Press your reset button to rescue it. One sentence: why does every real Johnson design include initialization or self-correction logic?
9. Wrap up. Complete the Analysis Questions and Knowledge Check, then Print/Save the report with your data tables.

📋 Data Tables

Predicted values go in before the simulation runs. Tables persist when you print this page.

Data Table 1 — 555 Astable (Part 1)

Data Table 2 — 555 Monostable (Part 2)

Data Table 3 — Self-Clocked '193 (Parts 3–4)

Data Table 4 — Johnson Counter (Part 5)

📈 Interactive Oscillator & Ring Playground

The lab's four personalities, live. In the 555 modes the canvas draws both scope channels — the capacitor's exponential shuttle between ⅓ and ⅔ V_CC, and the square output it produces — recalculated instantly as you swap components. The counter modes run from a simulated 555 so you can rehearse Parts 3–5 before wiring them.

✍ Analysis Questions

Answer in complete sentences in your lab report.

1. Using your Data Table 1 measurements: why can't the basic 555 astable reach exactly 50% duty cycle? Trace the answer to which resistors carry the charge and discharge currents, and state the standard design tactic for getting close to 50%.
2. Design problem: choose R_A, R_B, and C for a 1 kHz clock with duty near 52%. Show the calculation and check your values against the formula. (Many correct answers exist — justify yours.)
3. The 555's thresholds are ⅓ V_CC and ⅔ V_CC — ratios, not fixed voltages. Explain why this makes the astable's frequency almost independent of supply voltage, and why that mattered to designers in 1972 and still does.
4. Your monostable ignored how long the button was held (up to T). Name two real systems that need exactly this "stretch a messy input into one clean timed pulse" behavior, and identify R and C's role in each.
5. From Data Table 4: prove the Johnson counter's MOD is 2n rather than 2ⁿ, and compute how many flip-flops a Johnson counter needs for 16 states versus a binary counter. What does the Johnson buy for that extra hardware? (Your one-AND decode from step 7 is the answer.)
6. Your illegal-state experiment stranded the ring in a parallel orbit of 8 unused states. Design (describe or sketch) a self-correcting fix: a gate circuit that detects an illegal pattern — for example, a 0 sandwiched between 1s, i.e. Q1·Q̄2·Q3 — and pulses the CLR̄ line. Why is designing for states that "should never happen" a core engineering discipline?
7. Security connection: fault-injection attacks called clock glitching deliberately disturb a processor's oscillator — inserting runt pulses or momentary frequency spikes — so that instructions misexecute and security checks get skipped. Your Part 1 clock is external, exposed, and easy to touch; secure microcontrollers instead use internal oscillators plus clock-monitor circuits that detect out-of-range periods (a watchdog you could build from your Part 2 one-shot: retrigger it every cycle, and if a pulse ever fails to arrive, its timeout raises an alarm). Explain (a) why an attacker with access to a device's clock pin effectively holds a skeleton key to its logic, and (b) how the monostable-as-watchdog detects a stopped or stretched clock. What does this add to the Counters lab's lesson that security can live in hardware structure itself?

Key Facts Reference Box

Interactive Knowledge Check