Codes, Routes & Conversions: Where Digital Meets the World

Learning Objectives

Key Terms & Concepts

🖥 Tinkercad Setup Notes: Building What the Library Doesn't Stock

Seventh lab, and by now the pattern is the point: Tinkercad's library carries some of these functions as chips and omits others — and the omissions become the best builds. Here's the inventory honestly mapped:

• What Tinkercad HAS: the CD4511 BCD-to-7-segment decoder/driver (functional twin of the 74HC4511; the classic 74xx part is the 7447 — pinout documented in tab ②), the 7-segment display (common cathode), the 74HC193 up/down counter you'll meet again in the counters lab, and all your gate chips and LM741s from previous labs.
• What it LACKS: no 74HC138/139 decoder, no 74HC147/148 encoder, no 74HC151/157 MUX, no DAC0808, no ADC0804. Every one of those functions gets constructed in this lab from 74HC04/08/32 gates, plain resistors, and 741 comparators — and the commercial 74xx parts are documented alongside each build so you can translate to real hardware immediately.
• 7-segment display wiring: Tinkercad's common-cathode display needs its common pin(s) to GND and one 220 Ω resistor per segment (seven total) — not one shared resistor, which makes brightness vary with the digit. Hover each display pin: Tinkercad labels them a–g.
• R-2R ladder values: use 1 kΩ and 2 kΩ exactly. The ladder's magic depends on the 2:1 ratio, not the absolute values — but mixing tolerances breaks the binary weighting. Measure the output with the multimeter (V mode); it has effectively infinite input impedance in Tinkercad, so no buffering needed.
• Comparators for the flash ADC: three LM741s on a single +5 V/GND supply (pin 7 → +5 V, pin 4 → GND — no negative rail this time). Outputs won't reach the full rails (expect ≈1.5 V inside), which is why the ADC's indicators are LEDs driven directly rather than logic inputs. The optional binary-encoding step notes the level caveat.
• The pot is your analog signal: a 10 kΩ potentiometer across +5 V/GND, wiper = V_in, exactly as in the op-amp lab. Sweep it slowly and watch codes change in steps — that stepping IS quantization.

🔧 Virtual Parts List

📐 The Circuits You Will Build

Five figures for six builds — the demux shares Figure 1's circuit, because that identity is the lesson. Commercial 74xx equivalents are noted on every figure for translation to real hardware.

Commercial 74xx / Converter Reference

🛠 Step-by-Step Procedure

Session 1 = Parts 1–2 (decoders) · Session 2 = Parts 3–4 (encoder, MUX/DEMUX) · Session 3 = Parts 5–6 (DAC/ADC).

Part 1 — 2-to-4 Decoder from Gates (≈25 min)

1. Workspace. New circuit "LastName – Interface Lab." Breadboard, 5.00 V supply to rails. Two slide switches (SPDT harness) as inputs A1 and A0; four LED + 220 Ω indicators as Y0–Y3.
2. Seat the '04 and '08. Power ritual on both (14 → +5 V, 7 → GND). Wire A1 → 04 pin 1 and A0 → 04 pin 3; their outputs (pins 2, 4) are A̅1 and A̅0. Run A1, A̅1, A0, A̅0 to four labeled distribution columns.
3. Wire the four recognizers per Figure 1 on the '08: gate 1 (pins 1,2→3) gets A̅1, A̅0 → Y0; gate 2 (4,5→6) gets A̅1, A0 → Y1; gate 3 (9,10→8) gets A1, A̅0 → Y2; gate 4 (12,13→11) gets A1, A0 → Y3.
4. One-hot verification. Simulate. Step the switches through 00, 01, 10, 11 and record which LED lights in Data Table 1. Acceptance test: exactly one LED per code, every code. Two LEDs ever lit at once means a distribution wire is crossed.
5. Think ahead. One sentence in the report: your computer's RAM has ~34 address bits. How many outputs would a full 34-to-2³⁴ decoder have? (This is why memory decoders are built in trees.)

Part 2 — The Applied Decoder: BCD → 7-Segment (≈25 min)

1. Seat the CD4511 (16-pin: V_DD = 16 → +5 V, GND = 8). Immediately tie the control pins: LT̄ (3) → +5 V, BL̄ (4) → +5 V, LE (5) → GND. Skipping these is the #1 failure in this part.
2. Inputs. Four slide switches → the BCD pins in their scattered order: bit 0 → pin 7 (A), bit 1 → pin 1 (B), bit 2 → pin 2 (C), bit 3 → pin 6 (D). Label the switches on the workspace.
3. Display. Place the 7-segment (common cathode), its common pin → GND. Wire segment outputs through seven individual 220 Ω resistors: pin 13→a, 12→b, 11→c, 10→d, 9→e, 15→f, 14→g (hover the display's pins to match a–g).
4. Count 0 through 9. Enter each BCD code 0000–1001 and record the displayed digit in Data Table 2. Then try 1010–1111 (10–15): the 4511 blanks — note this, and contrast with what a hex-capable decoder would do.
5. Control-pin experiments. Momentarily ground LT̄ (all segments light — lamp test), ground BL̄ (display blanks), and raise LE with a digit showing, then change the switches (display freezes — LE is a latch, last lab's lesson hiding inside this chip). Record all three.

Part 3 — 4-to-2 Encoder from OR Gates (≈15 min)

1. Inputs and outputs. Four pushbuttons D0–D3, each with a 10 kΩ pull-down (button from +5 V to its column, resistor from column to GND). Two LEDs as the code output A1 (MSB), A0 (LSB).
2. Wire the '32 per Figure 3: gate 1 (pins 1,2→3): D1, D3 → A0. Gate 2 (4,5→6): D2, D3 → A1. D0 connects to nothing — pressing it yields code 00 by silence.
3. Verify. Press each button alone and record the 2-bit code in Data Table 3: D0→00, D1→01, D2→10, D3→11 — the exact inverse of Part 1.
4. Find the flaw. Press D1 and D2 together: the output claims 11, i.e. "D3" — a lie. Record it, and explain in one sentence what the 74HC148's priority logic would have answered instead (highest input wins: 10).

Part 4 — MUX, then the DEMUX Revelation (≈25 min)

1. Build the 2-to-1 MUX per Figure 3 with spare gates: inputs A and B from two slide switches, select S from a third; S → 04 spare inverter → S̄; AND gate 1: S̄·A; AND gate 2: S·B; OR them → Y → LED.
2. Prove selection. Set A = 1, B = 0. S = 0 → Y shows A (1). S = 1 → Y shows B (0). Now wiggle the unselected input and watch Y ignore it completely. Fill Data Table 4.
3. Route a live signal. Replace input B with the function generator (square, 1 Hz, 0–5 V). S = 1: the LED blinks (you routed the generator). S = 0: steady A. One wire = many sources, taking turns.
4. The demux revelation. Return to your Part 1 decoder. Pick ONE change: replace the A̅1·A̅0-style two-input recognition with three-input recognition by routing a DATA switch through spare '08 gates — concretely: take each decoder output Yn into a fresh AND gate paired with DATA, and move the LEDs to those gate outputs. Now A1 A0 select a destination and DATA's value appears there: 1-line-to-4-line demultiplexer. Toggle DATA with the code at 10 — only LED 2 blinks. Record in Data Table 4.
5. Say it in one sentence. For the report: why do 74HC138 datasheets title the chip "decoder/demultiplexer"?

Part 5 — R-2R DAC & the Staircase (≈30 min)

1. Build the ladder per Figure 4 on a clear breadboard area: backbone of three 1 kΩ resistors between four node columns; a 2 kΩ leg rising from each node to a slide switch (SPDT: GND / leg / +5 V); the 2 kΩ terminator from the LSB-end node to GND. Multimeter (V) from the MSB-end node (V_out) to GND.
2. Predict, then measure the corners. Predict with V_out = 5 × code/16, then measure codes 0000, 0001 (1 LSB!), 1000 (MSB alone = 2.5 V), 1111. Record predicted vs measured in Data Table 5.
3. Fill the table. Measure the remaining codes (order suggested in the table). The steps should march up by ≈0.3125 V each time. Any code that breaks the pattern → check that bit's 2 kΩ leg and switch.
4. Binary weight check. From your data: does code 1000 alone equal the sum of 0111 + 1 LSB? Show the arithmetic in the report — that identity is binary weighting, measured.
5. Automate: the staircase. Seat the 74HC193 (16-pin: V_CC 16, GND 8; tie CLR pin 14 → GND, LOAD pin 11 → +5 V, DOWN-clock pin 4 → +5 V). Function generator (square, 1 Hz, 0–5 V) → UP-clock pin 5. Replace the four switches: QA (pin 3) → b0 leg, QB (2) → b1, QC (6) → b2, QD (7) → b3. Oscilloscope on V_out, 500 ms/div.
6. Watch it climb. Run: V_out ascends 16 steps and wraps to zero — a staircase waveform, the counting of the '193 made visible as voltage. Sketch or screenshot it; record step height and period in Data Table 5. You have built a (slow) signal generator from a counter and eight resistors.

Part 6 — 2-Bit Flash ADC (≈30 min)

1. Reference ladder. Four 1 kΩ resistors in series from +5 V to GND. Verify the taps with the multimeter: 3.75 V, 2.50 V, 1.25 V top to bottom.
2. Comparator bank. Three LM741s, each powered single-supply: pin 7 → +5 V, pin 4 → GND. Wire each tap to one comparator's inverting input (pin 2): C1 gets 1.25 V, C2 gets 2.50 V, C3 gets 3.75 V.
3. Analog input. 10 kΩ pot across +5 V/GND; wiper → all three non-inverting inputs (pin 3), and → multimeter so you can read V_in precisely.
4. Thermometer display. Each comparator output (pin 6) → LED + 220 Ω → GND, stacked vertically L1 (bottom) to L3 (top).
5. Sweep and map. Turn the pot slowly from 0 to 5 V. The LEDs fill bottom-up — thermometer code. Record in Data Table 6 the V_in at which each LED turns on, versus the ladder's theoretical thresholds. Then park the pot at 1.8 V and nudge it ±0.2 V: the code doesn't move. You are standing inside one quantization step — that immobility is quantization error, experienced.
6. Optional: close the loop to binary. Route L1, L2, L3 into encoder logic (b1 = L2; b0 = L3 + (L1·L̄2) — one OR, one AND, one inverter from your spares) and two LEDs show the count 00–11 in binary. Note: the 741's HIGH (~3.5 V) is marginal for 74HC inputs; in Tinkercad it works — on real hardware you'd use an LM339 comparator with a pull-up. Record the binary column in Data Table 6.
7. Wrap up. Complete the Analysis Questions and Knowledge Check, then Print/Save your report with all six data tables.

📋 Data Tables

Tables persist when you print this page.

Data Table 1 — 2-to-4 Decoder (Part 1)

Data Table 2 — BCD → 7-Segment (Part 2)

Data Table 3 — 4-to-2 Encoder (Part 3)

Data Table 4 — MUX & DEMUX (Part 4)

Data Table 5 — R-2R DAC (Part 5)

Data Table 6 — Flash ADC (Part 6)

📈 Interactive Signal-Path & Conversion Playground

All six circuits, live. The digital modes draw the signal path with active routes in green; the converter modes plot the transfer function — the staircase that defines digital-analog conversion — with your operating point riding on it. Rehearse each part here before wiring it.

✍ Analysis Questions

Answer in complete sentences in your lab report.

1. State the input/output relationship of a decoder and an encoder in one sentence each, and use your Data Tables 1 and 3 to show they are inverses.
2. In Part 3 you caught the simple encoder lying when two buttons were pressed. Explain how the 74HC148's priority scheme resolves it, and give one real device where priority encoding is essential.
3. Defend the sentence "a demultiplexer is a decoder with data on its enable" using your Part 4 step 4 observations. Why do manufacturers sell one chip for both jobs?
4. From Data Table 5: compute the measured step size between consecutive codes and compare to the theoretical 1 LSB = 312.5 mV. Then compute what 1 LSB would be for an 8-bit and a 16-bit converter on the same 5 V reference — and explain what those numbers mean for audio quality.
5. Your staircase generator (counter + DAC) is a primitive arbitrary-waveform generator. Describe what waveform you'd get if the '193 counted down instead, and what you'd get alternating up/down.
6. Flash conversion needed 3 comparators for 2 bits. Derive the comparator count for n bits, evaluate it for 8 and 10 bits, and explain the engineering trade this architecture makes (and why oscilloscope front-ends pay it gladly).
7. Security connection: sensor-spoofing attacks target exactly the boundary you built in Part 6 — if an attacker can nudge V_in across one comparator threshold, the digital system downstream sees a different "fact." Using your Data Table 6 thresholds, state the minimum voltage perturbation that changes your ADC's output code, and explain in two sentences why more bits of resolution can make such tampering both harder to hide and easier to detect.

Key Facts Reference Box

Interactive Knowledge Check