Learning Objectives
By the end of this lab, you will be able to:
- Distinguish combinational logic (output depends only on present inputs) from sequential logic (output depends on input history), and identify feedback as the structural ingredient that creates memory.
- Construct an active-LOW SR latch from two cross-coupled 74HC00 NAND gates, characterize its SET, RESET, and HOLD states, and demonstrate the forbidden input combination and why it's disallowed.
- Extend the SR latch into a gated (transparent) D latch using the remaining two gates of the same 74HC00, and describe transparency: while the enable is HIGH, Q follows D; when it drops, Q freezes.
- Operate the 74HC74 dual D flip-flop: wire its clock, data, and active-LOW preset/clear pins correctly, and contrast edge-triggered capture (Q updates only at the rising clock edge) with latch transparency.
- Verify the asynchronous behavior of PRE̅ and CLR̄ — they override the clock entirely — and state why asynchronous controls exist.
- Synthesize a JK flip-flop around the 74HC74 using the characteristic equation D = J·Q̄ + K̄·Q with 74HC08/32/04 gates, and confirm all four behaviors: hold, reset, set, and toggle.
- Convert the JK into a T flip-flop (tie J = K = T), and demonstrate divide-by-two: with T = 1 and a 2 Hz clock, Q blinks at exactly 1 Hz — the seed of every binary counter.
Key Terms & Concepts
Click any card to reveal its definition. Review these before you build.
Memory Fundamentals
Sequential Logic
Memory Fundamentals
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Definition
Circuits whose output depends on present inputs and past history. The mechanism is feedback: an output routed back to an input lets the circuit hold a state. Every register, counter, and byte of RAM is sequential logic; every gate circuit from the previous lab was combinational.Latch vs Flip-Flop
Memory Fundamentals
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Definition
Both store one bit; the difference is when they listen. A latch is level-sensitive — transparent whenever its enable is active. A flip-flop is edge-triggered — it samples its inputs only at the instant the clock transitions, and ignores them the rest of the time.Q and Q̄
Memory Fundamentals
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Definition
The stored bit and its complement, both brought out as outputs. In every valid state they disagree — Q = 1, Q̄ = 0 or vice versa. The one condition that makes them agree is the SR latch's forbidden input, which is exactly why it's forbidden.Clock & Rising Edge
Memory Fundamentals
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Definition
The heartbeat of sequential systems: a square wave whose rising edge (LOW→HIGH transition) tells every flip-flop "sample now." Edge-triggering is what lets millions of flip-flops in a CPU update in lockstep once per cycle — your laptop's GHz rating counts these edges.The Four Devices
SR Latch
The Four Devices
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Definition
Two cross-coupled NAND gates: S̄et forces Q = 1, R̄eset forces Q = 0, both inactive = hold (memory!). Active-LOW in the NAND version: pulling an input to 0 activates it. The atom of storage — everything else in this lab is an SR latch wearing extra logic.D Latch / D Flip-Flop
The Four Devices
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Definition
One data input, no forbidden state: steering logic guarantees S and R are never both active. The latch (level) copies D to Q while enabled; the flip-flop (edge, e.g. 74HC74) copies D to Q only at the clock edge: Qnext = D. The workhorse of registers and pipelines.JK Flip-Flop
The Four Devices
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Definition
The SR idea with the forbidden state repurposed: J=K=1 means toggle (Q flips). Full characteristic: 00 hold · 01 reset · 10 set · 11 toggle. Characteristic equation Qnext = J·Q̄ + K̄·Q — which is precisely the formula you'll wire in Part 4.T Flip-Flop
The Four Devices
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Definition
A JK with J and K tied together as one input, Toggle: T = 0 hold, T = 1 flip on every clock edge. With T = 1 its output runs at exactly half the clock frequency — chain n of them and you've built a divide-by-2ⁿ binary counter, next lab's opening move.Practical Realities
Forbidden / Invalid State
Practical Realities
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Definition
Both SR inputs active at once: the NAND latch drives Q = Q̄ = 1 (they're supposed to disagree!), and worse, releasing both inputs simultaneously leaves the final state to a race the datasheet won't promise. You'll create it deliberately in Part 1 — in simulation, where it's free.Asynchronous PRE̅ / CLR̄
Practical Realities
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Definition
Override pins on the 74HC74 that force Q = 1 (preset) or Q = 0 (clear) immediately, ignoring the clock. Active-LOW: tie them HIGH for normal clocked operation. Their real job: putting a system into a known state at power-up — a reset button is a wire to CLR̄.Switch Bounce
Practical Realities
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Definition
A real pushbutton's contacts chatter for milliseconds on each press — dozens of edges where you intended one. Tinkercad's buttons are ideally clean, so your manual clock works perfectly here; on a physical bench the same circuit counts wildly until you add a debouncer. (Classic debouncer? An SR latch. This lab eats its own tail.)Characteristic Table
Practical Realities
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Definition
The sequential cousin of the truth table: inputs on the left, but the output column is Qnext — often written in terms of the present Q ("hold," "toggle"). Reading and filling characteristic tables is this lab's core measurement skill.🖥 Tinkercad Setup Notes for Sequential Circuits
Sixth lab — your gates-lab chips return, joined by one new IC and a new instrument habit:
- The one new chip: search "74HC74" — dual D flip-flop with preset and clear. Tinkercad has it. Pinout in tab ③ below: flip-flop #1 uses pins 1–6, power at the usual corners (14/7).
- No JK or T chip in Tinkercad: the library has no 7473/7476/74109. Parts 4–5 therefore build JK and T around the 74HC74 using the 74HC08, 74HC32, and 74HC04 from the Logic Gates lab — the characteristic equation wired literally. Third lab in a row where a library gap becomes the best exercise in the lab.
- Inputs: the same SPDT slide-switch harness as the gates lab for S̄/R̄/D/J/K/T (solid HIGH or LOW, never floating). For the clock, use a pushbutton with a 10 kΩ pull-down: button between +5 V and the clock pin, resistor from clock pin to GND. Press = one clean rising edge. (Clean only because Tinkercad buttons don't bounce — see the key-terms card.)
- Auto-clock for Part 5: the function generator, square wave, 2 Hz, 0–5 V (set amplitude/offset so the wave swings 0→5 V, not ±5 V — verify on the scope; negative voltages are out of spec for logic inputs). Slow enough to watch LEDs blink.
- Outputs: two LED + 220 Ω indicators, on Q and Q̄ — watching them trade places (and, once, illegally agree) is half the lab. Part 5 adds a third LED on the clock itself.
- Unused 74HC74 pins are not optional: tie PRE̅ (pin 4) and CLR̄ (pin 1) HIGH when you're not using them. Left floating, they'll randomly preset/clear your flip-flop — the sequential version of the floating-input lesson.
New Discipline: Order Matters Now
In combinational labs you could set switches in any order and read the answer. Not anymore. The same inputs can produce different outputs depending on the state you arrived in — that's what memory means. Follow the procedure's input sequences exactly, and record rows in the order performed. When a table asks for "Q before," write it down before touching anything.
🔧 Virtual Parts List
| Qty | Component (Tinkercad name) | Setting / Part | Used In |
|---|---|---|---|
| 1 | Breadboard (small) | — | All parts |
| 1 | Power Supply | 5.00 V | Logic supply, all parts |
| 2 | Slideswitch | SPDT: GND / input / 5 V | S̄ R̄ · D · J K · T inputs |
| 1 | Pushbutton + 10 kΩ | pull-down to GND | Manual clock, Parts 3–5 |
| 1 | Function Generator | square · 2 Hz · 0–5 V | Auto-clock, Part 5 |
| 1 | 74HC00 | quad NAND | SR latch (Part 1) · D latch (Part 2) |
| 1 | 74HC74 | dual D flip-flop | Parts 3–5 |
| 1 ea | 74HC08 · 74HC32 · 74HC04 | AND · OR · NOT | JK steering logic (Parts 4–5) |
| 3 | LED + Resistor 220 Ω | red (Q) · green (Q̄) · yellow (CLK) | State indicators |
| 1 | Multimeter / Oscilloscope | V mode / 100 ms/div | Levels · divide-by-2 waveforms |
| ~18 | Wires | red / black / green | All parts |
📐 The Circuits You Will Build
Four builds, one lineage: the cross-coupled NAND pair is the atom; everything after it is that atom plus steering logic. Watch the family resemblance as you move through the tabs.
Figure 1 — SR latch: gates 1 and 2 of a 74HC00. Each NAND's output feeds the other's second input (red wires). That loop is the entire secret: whichever gate wins holds the other down — one stored bit, no clock, no capacitor. The crossing wires look tangled on a breadboard; wire G1's output to G2's input first, then the reverse.
Figure 2 — Gated (transparent) D latch, all four gates of the same 74HC00. Steering gates G3/G4 translate the single D input into S̄/R̄ commands — and because D and its complement can never both be active, the forbidden state is engineered out. Note where G4's input comes from: G3's output, which supplies D̄.
Figure 3 — The 74HC74. Two independent edge-triggered D flip-flops; this lab uses #1 (pins 1–6). The active-LOW PRE̅ and CLR̄ must be tied HIGH for clocked operation — and in Part 3 you'll ground each one briefly to watch it seize control from the clock entirely.
Figure 4 — JK (and T) from parts. The 74HC08 computes J·Q̄ and K̄·Q, the 74HC32 combines them, and the result drives the 74HC74's D input; the red feedback wires close the loop from Q and Q̄. Every clock edge, the flip-flop captures "what JK behavior says comes next." Part 5 collapses J and K into a single T switch — no rewiring of the logic, just one jumper.
Characteristic Tables at a Glance
| Device | Inputs | Q_next | Behavior | Listens… |
|---|---|---|---|---|
| SR latch (NAND) | S̄=1 R̄=1 | Q | hold (memory) | always (level) |
| S̄=0 R̄=1 | 1 | set | ||
| S̄=1 R̄=0 | 0 | reset | ||
| S̄=0 R̄=0 | 1 = Q̄ ⚠ | forbidden | ||
| D latch | EN=1 | D | transparent | while EN high |
| EN=0 | Q | hold | ||
| D flip-flop (74HC74) | D | D | capture at edge | rising edge only |
| JK flip-flop | J=0 K=0 | Q | hold | rising edge only |
| J=0 K=1 | 0 | reset | ||
| J=1 K=0 | 1 | set | ||
| J=1 K=1 | Q̄ | toggle | ||
| T flip-flop | T=0 | Q | hold | rising edge only |
| T=1 | Q̄ | toggle → ÷2 |
SR: memory by feedback D: Q_next = D JK: Q_next = J·Q̄ + K̄·Q T: Q_next = T⊕Q T=1 → f(Q) = f(CLK) / 2
🛠 Step-by-Step Procedure
Suggested split: Session 1 = Parts 1–3 (latches + the 74HC74). Session 2 = Parts 4–5 (JK/T build + divide-by-2) + analysis. Remember the new discipline: perform sequences in order, record "Q before" before touching anything.
Part 1 — The SR Latch: Memory from Two Gates (≈25 min)
- Create the workspace. New circuit named "LastName – FlipFlop Lab." Small breadboard, Power Supply at 5.00 V to the rails.
- Input/output harness. Two SPDT slide switches (gates-lab wiring: GND / middle-to-column / +5 V) labeled S̄ and R̄ — start both slid HIGH. Two LED + 220 Ω indicators on columns Q (red) and Q̄ (green).
- Seat the 74HC00. Notch ritual, then pin 14 → +5 V, pin 7 → GND.
- Cross-couple gates 1 and 2. Per Figure 1: S̄ → pin 1; pin 6 (G2 out) → pin 2; G1's output pin 3 → column Q. Then R̄ → pin 5; pin 3 (G1 out) → pin 4; G2's output pin 6 → column Q̄. The two "crossing" wires are the memory — double-check them.
- Power-up state. Start the simulation with S̄ = R̄ = 1 and look: one LED is on, the other off — but which one wasn't commanded by you. Note it in Data Table 1 row 0. (Real hardware powers up randomly too; that's what CLR̄ pins are for, coming in Part 3.)
- Walk the sequence. Perform these steps in order, recording Q before and after each into Data Table 1: (a) S̄→0 (SET) · (b) S̄→1 (hold — Q remembers!) · (c) R̄→0 (RESET) · (d) R̄→1 (hold again) · (e) S̄→0 then back — set again. Step (b) is the moment of the lab: both inputs inactive, yet the circuit knows what happened last.
- Visit the forbidden state. Slide both S̄ and R̄ to 0: both LEDs light — Q = Q̄ = 1, a contradiction in terms. Record it. Then release both to 1 as simultaneously as you can and note which state it lands in; repeat twice and see if it's consistent. Write one sentence on why designers simply outlaw this input.
Part 2 — The Gated D Latch: Same Chip, Two More Gates (≈15 min)
- Add the steering gates. Keep the cross-coupled pair. Per Figure 2, wire gates 3 and 4 of the same 74HC00: relabel switch S̄ as D → pin 9; relabel R̄ as EN → pin 10 and pin 12; G3's output pin 8 → pin 13 and to the latch input that was S̄ (pin 1); G4's output pin 11 → the latch input that was R̄ (pin 5).
- Transparency test. EN = 1: wiggle D up and down — Q follows instantly, like a wire. Record three rows in Data Table 2.
- Hold test. Set D = 1 so Q = 1, then drop EN = 0. Now wiggle D wildly: Q ignores you. The latch froze the last value it saw. Record. Try to reach the forbidden state with any D/EN combination — you can't. One sentence: what does the steering logic guarantee?
Part 3 — The 74HC74: Edge Triggering & Async Overrides (≈25 min)
- Fresh build. Clear the NAND circuit (or slide it aside). Seat the 74HC74: pin 14 → +5 V, pin 7 → GND, and immediately tie pin 1 (CLR̄) and pin 4 (PRE̅) → +5 V.
- Clock button. Pushbutton from +5 V to pin 3, with 10 kΩ from pin 3 down to GND. Each press = one clean rising edge.
- Data and outputs. D switch → pin 2; pin 5 (Q) → red LED; pin 6 (Q̄) → green LED.
- The edge demonstration. Set D = 1. Nothing happens — and keep watching while you flip D back and forth a few times: still nothing. Now set D = 1 and press the clock: Q snaps to 1 at the press. Set D = 0, wait, press: Q → 0. The flip-flop listens for one instant per press. Fill Data Table 3's clocked rows, and contrast in writing with Part 2's transparency.
- Change-D-between-edges test. With Q = 0: set D = 1, then D = 0, then D = 1 again without clocking, then press. Which D value got captured? (The one present at the edge — history between edges is invisible.)
- Async overrides. With Q = 0 and no clocking: momentarily ground pin 4 (PRE̅) — Q jumps to 1 instantly, no clock involved. Restore pin 4 HIGH. Now momentarily ground pin 1 (CLR̄) — Q drops to 0 instantly. Record both in Data Table 3's async rows, and note in one sentence what a system "reset button" really is.
Part 4 — Build the JK Flip-Flop (≈25 min)
- Add the steering chips. Seat the 74HC08 (AND), 74HC32 (OR), and 74HC04 (NOT) near the '74. Power ritual on all three (14/7 each).
- Wire the characteristic equation per Figure 4: J switch → 08 pin 1; Q̄ (74 pin 6) → 08 pin 2 — first AND computes J·Q̄ at pin 3. K switch → 04 pin 1; K̄ (04 pin 2) → 08 pin 4; Q (74 pin 5) → 08 pin 5 — second AND computes K̄·Q at pin 6. Both AND outputs → 32 pins 1 and 2; OR output pin 3 → 74 pin 2 (D). Clock button stays on 74 pin 3.
- Verify all four behaviors. For each row of Data Table 4, set J and K, note Q before, press the clock once, record Q after: 00 → hold · 01 → reset · 10 → set · 11 → toggle. Do the 11 row three presses in a row: Q alternates every single press.
- Convince yourself with the equation. Pick your 11-toggle row and evaluate D = J·Q̄ + K̄·Q by hand for Q = 0 and Q = 1. The algebra predicts the flip. Attach the two-line calculation to your report.
Part 5 — T Flip-Flop & Divide-by-Two (≈15 min)
- Make it a T. One jumper: tie the J and K switch columns together and drive both from a single switch, now labeled T. Verify: T = 0 + clock presses → nothing; T = 1 + presses → toggle every press. Record in Data Table 5.
- Auto-clock. Replace the button with the function generator: square, 2 Hz, 0–5 V (verify 0-to-5 swing on the scope first). Add the yellow LED + 220 Ω on the clock line itself.
- Watch the division. T = 1, run: the yellow (clock) LED blinks 2× per second; the red (Q) LED blinks once per second — every rising edge toggles Q, and two toggles make one full Q cycle. Put both signals on oscilloscopes: Q's period is exactly double the clock's. Record both frequencies in Data Table 5.
- The bridge to counters. One sentence for the report: if Q fed the clock of a second T flip-flop, what frequency would its output blink at? (You just designed the next lab.)
- Wrap up. Complete the Analysis Questions and Knowledge Check, then Print/Save the report with your data tables.
Troubleshooting
SR latch: both LEDs dim or flickering? A cross-coupling wire is missing — without full feedback there's no latch, just gates. 74HC74 ignores the clock? PRE̅ or CLR̄ is floating or grounded — both must be tied HIGH (pins 1 and 4). Q changes while D changes, no clock pressed? You're on the latch build, not the '74 — or the button is wired always-closed. JK toggle unreliable? Check the two feedback wires: J's AND partner must be Q̄ (pin 6), K̄'s must be Q (pin 5). Swapped feedback gives set/reset that "work" and a toggle that doesn't. Divide-by-2 LED blinks erratically? Scope the generator: if it swings ±5 V instead of 0–5 V, fix amplitude/offset.
📋 Data Tables
Sequential circuits care about order — fill rows top to bottom as performed. Tables persist when you print this page.
Data Table 1 — SR Latch Sequence (Part 1)
| Step | S̄ | R̄ | Q before | Q after | Q̄ after | State name |
|---|---|---|---|---|---|---|
| 0 · power-up | 1 | 1 | — | |||
| a · set | 0 | 1 | ||||
| b · release S̄ | 1 | 1 | ||||
| c · reset | 1 | 0 | ||||
| d · release R̄ | 1 | 1 | ||||
| e · forbidden | 0 | 0 | ||||
| f · release both | 1 | 1 | ⚠ |
Data Table 2 — D Latch Transparency (Part 2)
| EN | D | Q | Mode |
|---|---|---|---|
| 1 | 0 | ||
| 1 | 1 | ||
| 1 | 0 | ||
| 0 | 1 | ||
| 0 | 0 |
Data Table 3 — 74HC74 D Flip-Flop (Part 3)
| Action | D | PRE̅ | CLR̄ | Q before | Q after |
|---|---|---|---|---|---|
| D=1, no clock (wiggle) | 1↔0 | 1 | 1 | ||
| D=1, clock press ▲ | 1 | 1 | 1 | ||
| D=0, clock press ▲ | 0 | 1 | 1 | ||
| D wiggled 1-0-1, then ▲ | 1 @ edge | 1 | 1 | ||
| PRE̅ grounded (async) | × | 0 | 1 | ||
| CLR̄ grounded (async) | × | 1 | 0 |
Data Table 4 — JK Flip-Flop Build (Part 4)
| J | K | Q before | Q after ▲ | Behavior |
|---|---|---|---|---|
| 0 | 0 | |||
| 0 | 1 | |||
| 1 | 0 | |||
| 1 | 1 | |||
| 1 | 1 | |||
| 1 | 1 |
Data Table 5 — T Flip-Flop & Divide-by-Two (Part 5)
| Condition | Result |
|---|---|
| T = 0, three clock presses → Q does… | |
| T = 1, three clock presses → Q does… | |
| Clock (yellow LED) frequency | |
| Q (red LED) frequency | |
| Ratio f(CLK) : f(Q) |
📈 Interactive Flip-Flop Playground with Timing Diagram
A live twin of every build in this lab. Pick a device, work its inputs, and watch the timing diagram grow — each button action appends one time step, so the canvas becomes a record of the exact sequence you performed. Use it to rehearse each procedure sequence before wiring it, and to see why "the same inputs" can give different outputs.
What To Notice
On the D latch, raise EN and wiggle D: Q's trace mirrors D step for step. Drop EN and wiggle D again: Q's trace goes flat while D dances above it — transparency versus hold, drawn. Then switch to the D FF and wiggle D without clocking: Q never moves until a ▲ column appears. Finally set the JK to 11 and pulse repeatedly — Q's trace becomes a square wave at half the pulse rate. You're looking at the divide-by-2 of Part 5, one press at a time.
✍ Analysis Questions
Answer in complete sentences in your lab report.
- Using Data Table 1 steps (b) and (d): the inputs were identical (S̄ = R̄ = 1) but Q differed. Explain, in terms of feedback, how the circuit "knows" which state to hold.
- Why is S̄ = R̄ = 0 forbidden for the NAND latch? Address both problems: the state itself, and what happens when the inputs are released together.
- Contrast your Part 2 and Part 3 observations: describe one situation where a transparent latch would corrupt data that an edge-triggered flip-flop would handle correctly. (Hint: what happens if D changes twice while EN is high?)
- In Part 3 step 6, PRE̅ and CLR̄ overrode the clock. Explain why every real system needs at least one asynchronous control, using power-up as your example.
- Evaluate D = J·Q̄ + K̄·Q for all four JK input combinations (with Q as a variable), and show the results reproduce hold / reset / set / toggle.
- From Part 5: a chain of four T flip-flops (each Q clocking the next) is driven at 16 Hz. Give the output frequency of each stage, and state the general rule for n stages.
- Security connection: a linear-feedback shift register (LFSR) — the keystream engine inside many stream ciphers — is a row of D flip-flops whose input is an XOR of taps from the row. Using this lab plus the gates lab, list the chips you'd need to build a 4-bit LFSR in Tinkercad, and explain in one sentence why the flip-flops (not the XOR) are what give the cipher its state.
Key Facts Reference Box
Memory mechanism
Feedback: outputs re-enter as inputs
Latch vs flip-flop
Level-sensitive vs edge-triggered
NAND SR latch inputs
Active LOW · both 0 = forbidden
D latch, EN = 1
Transparent: Q follows D
74HC74 FF #1 pins
CLR̄ 1 · D 2 · CLK 3 · PRE̅ 4 · Q 5 · Q̄ 6
PRE̅ / CLR̄
Async, active LOW — tie HIGH normally
JK characteristic equation
Q_next = J·Q̄ + K̄·Q
JK = 11
Toggle — the forbidden state, tamed
T flip-flop
JK with J = K · T=1 → divide by 2
n-stage T chain
f_out = f_clock / 2ⁿ → binary counter
Interactive Knowledge Check
Six questions drawn directly from the lab. Select an answer for each, then press Grade My Quiz.