⚑ ELT 102 · Digital Logic & Solid State Devices Hands-On Tinkercad Lab
Unit 1 Β· Digital Logic Β· Lab

Logic Gates in Silicon: The 74xx Family

Wire real integrated circuits β€” 74HC00, 02, 04, 08, 32, and 86 β€” into a reusable test bench in Autodesk Tinkercad Circuits. Derive the truth table of every two-input gate by direct measurement, dodge the famous 7402 pinout trap, and build the one gate Tinkercad doesn't give you: XNOR, from parts.

⏱ 2 Γ— 75-Minute Sessions πŸ–₯ Tinkercad Circuits (Free) πŸ”§ 6 Chips Β· 7 Gates Β· 1 Test Bench πŸ“Š Interactive Gate Playground βœ… 6-Question Knowledge Check

Learning Objectives

By the end of this lab, you will be able to:

  • Construct a reusable logic test bench in Tinkercad β€” switch-driven inputs, LED output indicator, and a socketed gate under test β€” and use it to characterize six different 74xx-family ICs.
  • Determine the complete truth table of AND, OR, NAND, NOR, XOR, XNOR, and NOT gates by direct measurement, recording one row per input combination.
  • Interpret 14-pin DIP pinout diagrams: locate pin 1 from the notch, apply the counterclockwise numbering convention, and wire VCC (pin 14) and GND (pin 7) on every chip before anything else.
  • Contrast the standard quad-gate pinout (74HC00/08/32/86: inputs 1,2 β†’ output 3) with the reversed 74HC02 NOR pinout (output 1 ← inputs 2,3), and explain why datasheet verification beats assumption.
  • Write the Boolean expression for each gate (AΒ·B, A+B, AΒ·B, A+B, AβŠ•B, AβŠ•B, A) and match expressions to measured behavior.
  • Synthesize an XNOR function from a 74HC86 XOR gate and a 74HC04 inverter, demonstrating that gates compose into new functions.
  • Demonstrate NAND's universality by building a working NOT and AND from 74HC00 gates alone, and explain why defined logic levels (never floating inputs) matter in real hardware.

Key Terms & Concepts

Click any card to reveal its definition. Review these before you build.

Digital Fundamentals
Logic Gate
Digital Fundamentals
πŸ”„ Click to reveal definition
Definition
A circuit that implements a Boolean function: inputs and output are restricted to two states, HIGH (1) and LOW (0). Under the hood, each gate is a handful of the transistors you met in the BJT lab, arranged as saturating switches.
Logic Levels (HIGH / LOW)
Digital Fundamentals
πŸ”„ Click to reveal definition
Definition
Voltage ranges that count as 1 and 0. For a 5 V 74HC chip, roughly: above ~3.5 V reads HIGH, below ~1.5 V reads LOW. Everything between is undefined β€” the no-man's-land your switches must cross quickly and never park in.
Truth Table
Digital Fundamentals
πŸ”„ Click to reveal definition
Definition
The gate's complete rΓ©sumΓ©: every input combination and the output each produces. A two-input gate has exactly 2Β² = 4 rows; measure all four and you know everything the gate can ever do. This lab is truth-table archaeology, chip by chip.
Boolean Expression
Digital Fundamentals
πŸ”„ Click to reveal definition
Definition
Algebra for logic: AND is multiplication (AΒ·B), OR is addition (A+B), NOT is the overbar (A), XOR is βŠ•. Every circuit in this lab has a one-line expression β€” and every expression you'll write in later combinational-logic work compiles down to gates like these.
The Chips
74xx Family
The Chips
πŸ”„ Click to reveal definition
Definition
The most famous logic IC series ever made, born as TTL in the 1960s and still shipping. The last digits name the function: 00 NAND Β· 02 NOR Β· 04 NOT Β· 08 AND Β· 32 OR Β· 86 XOR. Tinkercad's parts are the 74HC (high-speed CMOS) versions β€” same pinouts, same logic.
DIP Package & Pin 1
The Chips
πŸ”„ Click to reveal definition
Definition
Dual In-line Package: two rows of pins straddling the breadboard trench. Find the notch (or dot); pin 1 is immediately counterclockwise of it, and numbering runs counterclockwise around the chip. For all 14-pin chips in this lab: GND = pin 7, VCC = pin 14 β€” the diagonal corners.
Quad 2-Input Package
The Chips
πŸ”„ Click to reveal definition
Definition
Each 14-pin gate chip holds four identical, independent gates (the 7404 holds six inverters). You'll use gate #1 (pins 1–3) throughout, but any of the four works β€” a fact that saves real boards when one gate section dies.
The 7402 Pinout Trap
The Chips
πŸ”„ Click to reveal definition
Definition
On the 00/08/32/86, each gate reads inputs 1,2 β†’ output 3. The NOR chip alone is mirrored: output on pin 1, inputs on pins 2,3. Wire it by habit and your "NOR" produces nonsense. The lab's standing lesson: the datasheet, not the pattern, is the authority.
Gate Behavior
XOR: The Difference Detector
Gate Behavior
πŸ”„ Click to reveal definition
Definition
Output HIGH only when the inputs disagree. Equivalently: a 1-bit adder's sum, a controllable inverter, a parity generator. XNOR is its complement β€” HIGH when inputs match β€” which makes it a 1-bit equality comparator.
Universal Gates
Gate Behavior
πŸ”„ Click to reveal definition
Definition
NAND (and NOR) can each build every other logic function. Tie a NAND's inputs together β†’ NOT. Follow a NAND with that NOT β†’ AND. Entire processors have been built from a single gate type β€” Part 5 gives you a taste.
Floating Input
Gate Behavior
πŸ”„ Click to reveal definition
Definition
An input connected to nothing. It doesn't read as 0 β€” it reads as whatever stray charge says, drifting and flickering (CMOS inputs are so high-impedance they'll follow your hand's electric field). Rule: every input gets a defined level, always. Our SPDT slide switches guarantee it.
Active-HIGH Indicator
Gate Behavior
πŸ”„ Click to reveal definition
Definition
Our output LED (through 220 Ξ© to ground) lights when the gate output is HIGH β€” so LED ON = logic 1, directly. Keep the convention in mind when reading tables: the LED is a 1-bit display, and you are the analog-to-digital converter.

πŸ–₯ Tinkercad Setup Notes for Logic ICs

Fifth lab, familiar toolkit β€” new part family:

The One Habit This Lab Exists to Teach
Before wiring any IC: find the notch β†’ identify pin 1 β†’ confirm power pins β†’ confirm the gate's input/output pins against the pinout diagram. Thirty seconds of ritual. The 74HC02 in Part 2 is deliberately included because it punishes anyone who skips it.

πŸ”§ Virtual Parts List

QtyComponent (Tinkercad name)Setting / PartPurpose
1Breadboard (small)β€”Test bench platform
1Power Supply5.00 VLogic supply to rails
2SlideswitchSPDT: GND / input / 5 VInputs A and B, never floating
1LED (red) + Resistor 220 Ξ©β€”Output indicator: ON = 1
1 ea74HC08 Β· 74HC32 Β· 74HC00 Β· 74HC02 Β· 74HC86quad 2-input gatesAND Β· OR Β· NAND Β· NOR Β· XOR
174HC04hex inverterNOT Β· XNOR build Β· NAND challenge
1MultimeterV modeMeasuring actual HIGH/LOW voltages
~12Wiresred / black / greenPower, ground, logic

πŸ“ The Test Bench & The Pinouts

One test bench, six chips. You build the switch-and-LED harness once; each new gate is a two-minute chip swap β€” provided you respect the pinouts.

+5 V GND SW A A SW B B gate under test (pins per tabs β‘‘ / β‘’) Y LED 220 Ξ© Chip power (every chip, first): pin 14 β†’ +5 V Β· pin 7 β†’ GND Switch wiring (each input): side 1 β†’ GND Β· side 2 β†’ +5 V middle β†’ gate input
Figure 1 β€” The reusable test bench. Two SPDT switches give solid HIGH/LOW inputs A and B; the LED reports output Y (ON = 1). Only the chip in the middle changes between Parts 1–3 β€” build the harness with a little slack in the wires so chip swaps are painless.
notch = pin-1 end 74HC00 Β· 08 32 Β· 86 1 Β· 1A (input) 2 Β· 1B (input) 3 Β· 1Y (OUTPUT) 4 Β· 2A 5 Β· 2B 6 Β· 2Y 7 Β· GND ⏚ 14 Β· V_CC (+5 V) 13 Β· 4B 12 Β· 4A 11 Β· 4Y 10 Β· 3B 9 Β· 3A 8 Β· 3Y Gate #1 = pins 1, 2 β†’ 3. Four independent gates per chip; this lab uses gate #1. Same map for AND, OR, NAND, and XOR chips.
Figure 2 β€” The standard quad-gate pinout. 74HC00 (NAND), 74HC08 (AND), 74HC32 (OR), and 74HC86 (XOR) all share this map: inputs 1 & 2, output 3. Power always at the diagonal corners: GND pin 7, VCC pin 14. One wiring pattern covers four of the six chips.
74HC02 quad NOR 1 Β· 1Y (OUTPUT!) 2 Β· 1A (input) 3 Β· 1B (input) 7 Β· GND 14 Β· V_CC ⚠ MIRRORED: output first. Gate #1 = pin 1 ← pins 2, 3. 74HC04 hex inverter 1 Β· 1A (input) 2 Β· 1Y (output) 3 Β· 2A 7 Β· GND 14 Β· V_CC 13 Β· 6A Six inverters: 1β†’2, 3β†’4, 5β†’6, 9β†’8, 11β†’10, 13β†’12.
Figure 3 β€” The two exceptions. The 74HC02 NOR mirrors the standard map β€” output on pin 1, inputs on 2 and 3. History says the layout simplified the original chip's internal routing; the lab says it's why engineers check datasheets. The 74HC04 packs six single-input inverters; only NOT uses one switch and needs just input A.
A B βŠ• 74HC86 gate 1 (pins 1, 2 β†’ 3) A βŠ• B 74HC04 inverter 1 (pin 1 β†’ 2) Y = A βŠ• B = XNOR to GND Both chips powered (14 β†’ +5 V, 7 β†’ GND). Inverting XOR's "inputs differ" gives XNOR's "inputs match" β€” a 1-bit equality tester.
Figure 4 β€” XNOR from parts. Tinkercad has no XNOR chip, so you compose one: 74HC86 pin 3 feeds 74HC04 pin 1; the inverter's pin 2 drives the LED. Predicted truth table: the exact complement of your measured XOR column.

The Seven Gates at a Glance

GateChipGate-1 pinsBooleanOutput is HIGH when…
AND74HC081, 2 β†’ 3Y = AΒ·Bboth inputs are 1
OR74HC321, 2 β†’ 3Y = A+Bat least one input is 1
NAND74HC001, 2 β†’ 3Y = AΒ·BNOT both 1 (AND inverted)
NOR74HC02 ⚠2, 3 β†’ 1Y = A+Bboth inputs are 0 (OR inverted)
XOR74HC861, 2 β†’ 3Y = AβŠ•Binputs differ
XNOR86 + 04 build3 β†’ 1 β†’ 2Y = AβŠ•Binputs match
NOT74HC041 β†’ 2Y = Athe (single) input is 0

πŸ›  Step-by-Step Procedure

Suggested split: Session 1 = Parts 1–2 (bench + the five quad-gate chips). Session 2 = Parts 3–5 + analysis.

Part 1 β€” Build the Test Bench + First Chip: AND (β‰ˆ30 min)

  1. Create the workspace. New circuit named "LastName – Logic Gates Lab." Small breadboard; Power Supply at 5.00 V to the bottom rails.
  2. Input switches. Place two Slideswitches left of the board. For each: terminal 1 β†’ GND rail, terminal 3 β†’ +5 V rail, middle terminal β†’ a labeled breadboard column (call them column A and column B). Slide each switch and verify with the multimeter: the middle terminal reads cleanly 0 V or 5 V.
  3. Output indicator. Reserve a column Y β†’ LED anode; cathode β†’ 220 Ξ© β†’ GND rail.
  4. Seat the 74HC08. Straddle the trench, notch to the left. Ritual: find the notch β†’ pin 1 below-left of it β†’ wire pin 14 β†’ +5 V, pin 7 β†’ GND β†’ hover-confirm pins 1, 2, 3 against Figure 2.
  5. Connect the harness. Column A β†’ pin 1, column B β†’ pin 2, pin 3 β†’ column Y.
  6. Measure the truth table. Start the simulation. Step through all four input combinations in binary order β€” 00, 01, 10, 11 β€” and record the LED state for each row in Data Table 1's AND column. Four rows, no skipping: two of them are where AND, NAND, and OR all look alike, and the other two are where they don't.
  7. Measure a real HIGH. With Y = 1, put the multimeter on pin 3: record the actual output voltage in Data Table 3. It won't be exactly 5.000 V β€” note what it is.

Part 2 β€” The Chip Parade: OR, NAND, XOR, then NOR (β‰ˆ30 min)

  1. Swap to the 74HC32 (OR). Stop the sim, delete only the chip, seat the 74HC32 in the same spot, re-wire power + pins 1/2/3 (same map). Measure all four rows into the OR column.
  2. Swap to the 74HC00 (NAND). Same drill. Before measuring, predict the column by inverting your AND results β€” then verify row by row.
  3. Swap to the 74HC86 (XOR). Same map again. Measure, and note in words when the LED lights.
  4. Now the 74HC02 (NOR) β€” read first. Open Figure 3. This chip is mirrored: inputs go to pins 2 and 3, output comes from pin 1. Wire it accordingly: A β†’ pin 2, B β†’ pin 3, pin 1 β†’ Y.
  5. Measure NOR into its column. Then, as a deliberate experiment: rewire it the standard way (A→1, B→2, 3→Y) for one input combination and observe the nonsense. Put the correct wiring back. You have now personally met the trap — record one sentence about what the wrong wiring produced.

Part 3 β€” NOT with the Hex Inverter (β‰ˆ10 min)

  1. Seat the 74HC04. Power ritual first. This gate has ONE input: column A β†’ pin 1, pin 2 β†’ Y. Switch B rests this round.
  2. Measure both rows (A = 0, A = 1) into Data Table 2. Then try one of the other five inverters on the chip (say pins 3 β†’ 4) to confirm the sections are identical and independent.

Part 4 β€” Build the Missing Gate: XNOR (β‰ˆ15 min)

  1. Two chips, both powered. Seat the 74HC86 and the 74HC04 side by side; give each its pin 14 / pin 7 power connections.
  2. Compose per Figure 4. A β†’ 86 pin 1, B β†’ 86 pin 2; 86 pin 3 β†’ 04 pin 1; 04 pin 2 β†’ Y.
  3. Predict, then measure. Write the predicted XNOR column (complement of your XOR data) first, then measure all four rows. The gate that wasn't in the library now exists on your bench.

Part 5 β€” Universal-Gate Challenge (β‰ˆ15 min, extension)

  1. NOT from NAND. On a fresh 74HC00: tie pins 1 and 2 together to column A; pin 3 β†’ Y. Measure both rows β€” you built an inverter from a NAND.
  2. AND from NAND. Keep gate 1 as a normal NAND (A→1, B→2). Route its output (pin 3) into gate 2's tied-together inputs (pins 4 and 5 jumpered); pin 6 → Y. Measure all four rows and compare to Part 1's AND column: identical, using only NANDs.
  3. Reflect. One paragraph: why does "NAND is universal" matter for how real chips and FPGAs are manufactured?
  4. Wrap up. Complete the Analysis Questions and Knowledge Check, then Print/Save the report with your data tables.
Troubleshooting
LED never changes? Check chip power first β€” pin 14 and pin 7 β€” then confirm the output pin actually routes to Y. Output flickers or drifts? An input is floating: a switch middle terminal isn't landing on the input column. NOR truth table looks wrong? You wired the 02 with the standard map β€” Figure 3. Everything works but backwards? Your LED is fine; check whether you accidentally grabbed the NAND instead of the AND chip (the labels matter more than the habit).

πŸ“‹ Data Tables

Record the LED state (1 = ON, 0 = OFF) for every row. The tables persist when you print this page.

Data Table 1 β€” Two-Input Gates (measured truth tables)

ABAND (08)OR (32)NAND (00)NOR (02)XOR (86)XNOR (86+04)
00
01
10
11

Data Table 2 β€” NOT & the NAND-Built Gates

ABNOT (04)NOT from NANDAND from 2Γ— NAND
00
01β€”β€”
10
11β€”β€”

Data Table 3 β€” Real Voltages Behind the 1s and 0s

MeasurementVoltageReads as
Output pin, LED ON (any gate)
Output pin, LED OFF
Switch middle terminal, slid HIGH

πŸ“ˆ Interactive Gate Playground

A live twin of your Tinkercad test bench. Pick a gate, click the input switches, and watch the symbol, the wires, the LED, and the truth-table highlight respond together. Use it to predict each row before you measure it on the breadboard β€” and afterward, to check your data tables.

What To Notice
Walk any gate through 00 β†’ 01 β†’ 10 β†’ 11 and watch the highlighted row descend the truth table β€” that binary counting order is the same discipline the procedure demands at the bench. Then compare NAND against AND at every step: the LED is always opposite. Finally, look at where the bubble sits on the N-gates' symbols: the bubble is the inversion, drawn.

✍ Analysis Questions

Answer in complete sentences in your lab report.

  1. Two of the four rows of your AND and OR columns are identical, and two differ. Identify which rows distinguish the gates, and explain why testing only "both LOW" and "both HIGH" would be an incomplete characterization of a mystery chip.
  2. Compare your NAND column to your AND column, and your NOR column to your OR column. State the relationship, then express it with a Boolean overbar.
  3. Describe what happened in the deliberate mis-wiring experiment of Part 2 step 5, and explain why the 74HC02's mirrored pinout produced that behavior rather than a clean "wrong gate."
  4. Your XNOR was built from two chips. Using your measured XOR data, prove (row by row) that the composite circuit had to produce the XNOR truth table.
  5. In Data Table 3, the "HIGH" output wasn't exactly 5.000 V, yet the logic worked perfectly. Explain how defined logic-level ranges make digital circuits immune to the small analog imperfections you measured β€” and why a floating input defeats that immunity.
  6. From Part 5: draw (or describe) how you would build an OR gate using only 74HC00 NAND gates. (Hint: De Morgan β€” invert both inputs first. How many NAND sections does it take?)
  7. A security-minded connection: XOR is the heart of stream ciphers and one-time pads because A βŠ• K βŠ• K = A. Using your measured XOR truth table, show why XORing with the same key twice returns the original bit.

Key Facts Reference Box

Chip numbers
00 NAND Β· 02 NOR Β· 04 NOT Β· 08 AND Β· 32 OR Β· 86 XOR
Power pins (14-pin DIP)
GND = 7 Β· V_CC = 14
Standard gate-1 pins
inputs 1, 2 β†’ output 3
74HC02 exception
output 1 ← inputs 2, 3
Pin 1 location
Counterclockwise from the notch
Rows in a 2-input truth table
2Β² = 4 Β· test in binary order
XOR / XNOR meaning
differ-detector / match-detector
Universal gates
NAND and NOR each build everything
NOT from NAND
tie both inputs together
Floating input
undefined β€” always tie HIGH or LOW

Interactive Knowledge Check

Six questions drawn directly from the lab. Select an answer for each, then press Grade My Quiz.

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